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Add CPSxx instructions, and some missing FPA instructions.

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git-svn-id: branches/laksen/armiw@29368 -
This commit is contained in:
Jeppe Johansen 2015-01-01 21:17:21 +00:00
parent ff7af306df
commit f963ff1b5b
4 changed files with 201 additions and 1 deletions
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54
compiler/arm/aasmcpu.pas
View File

@ -4133,6 +4133,26 @@ implementation
else
message(asmw_e_invalid_opcode_and_operands);
end;
#$46: { System instructions }
begin
{ set instruction code }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
bytes:=bytes or (ord(insentry^.code[3]) shl 8);
{ set regs }
if (oper[0]^.typ=top_modeflags) then
begin
if mfA in oper[0]^.modeflags then bytes:=bytes or (1 shl 8);
if mfI in oper[0]^.modeflags then bytes:=bytes or (1 shl 7);
if mfF in oper[0]^.modeflags then bytes:=bytes or (1 shl 6);
end;
if (ops=2) then
bytes:=bytes or (oper[1]^.val and $1F)
else if (ops=1) and
(oper[0]^.typ=top_const) then
bytes:=bytes or (oper[0]^.val and $1F);
end;
#$60: { Thumb }
begin
bytelen:=2;
@ -4440,6 +4460,19 @@ implementation
bytes:=bytes or (oper[0]^.val and $FF);
end;
end;
#$6C: { Thumb: CPS }
begin
bytelen:=2;
bytes:=0;
{ set opcode }
bytes:=bytes or (ord(insentry^.code[1]) shl 8);
bytes:=bytes or ord(insentry^.code[2]);
if mfA in oper[0]^.modeflags then bytes:=bytes or (1 shl 2);
if mfI in oper[0]^.modeflags then bytes:=bytes or (1 shl 1);
if mfF in oper[0]^.modeflags then bytes:=bytes or (1 shl 0);
end;
#$80: { Thumb-2: Dataprocessing }
begin
bytes:=0;
@ -5030,6 +5063,27 @@ implementation
message(asmw_e_invalid_effective_address);
end;
end;
#$8F: { Thumb-2: CPSxx }
begin
{ set opcode }
bytes:=bytes or (ord(insentry^.code[1]) shl 24);
bytes:=bytes or (ord(insentry^.code[2]) shl 16);
bytes:=bytes or (ord(insentry^.code[3]) shl 8);
bytes:=bytes or ord(insentry^.code[4]);
if (oper[0]^.typ=top_modeflags) then
begin
if mfA in oper[0]^.modeflags then bytes:=bytes or (1 shl 7);
if mfI in oper[0]^.modeflags then bytes:=bytes or (1 shl 6);
if mfF in oper[0]^.modeflags then bytes:=bytes or (1 shl 5);
end;
if (ops=2) then
bytes:=bytes or (oper[1]^.val and $1F)
else if (ops=1) and
(oper[0]^.typ=top_const) then
bytes:=bytes or (oper[0]^.val and $1F);
end;
#$A0: { FPA: CPDT(LDF/STF) }
begin
{ set instruction code }

20
compiler/arm/armins.dat
View File

@ -262,8 +262,22 @@ reg32,reg32 \x80\xFA\xB0\xF0\x80 THUMB32,ARMv6T2
reg32,reg32 \x32\x01\x6F\xF\x10 ARM32,ARMv4
[CPS]
immshifter \x8F\xF3\xAF\x81\x00 THUMB32,ARMv6T2
immshifter \x46\xF1\x2\x0\x0 ARM32,ARMv6
[CPSID]
modeflags \x6C\xB6\x70 THUMB,ARMv6
modeflags \x8F\xF3\xAF\x86\x00 THUMB32,WIDE,ARMv6T2
modeflags,immshifter \x8F\xF3\xAF\x87\x00 THUMB32,WIDE,ARMv6T2
modeflags \x46\xF1\xC\x0\x0 ARM32,ARMv6
modeflags,immshifter \x46\xF1\xE\x0\x0 ARM32,ARMv6
[CPSIE]
modeflags \x6C\xB6\x60 THUMB,ARMv6
modeflags \x8F\xF3\xAF\x84\x00 THUMB32,WIDE,ARMv6T2
modeflags,immshifter \x8F\xF3\xAF\x85\x00 THUMB32,WIDE,ARMv6T2
modeflags \x46\xF1\x8\x0\x0 ARM32,ARMv6
modeflags,immshifter \x46\xF1\xA\x0\x0 ARM32,ARMv6
[EORcc]
reglo,reglo \x6B\x40\x40 THUMB,ARMv4T
@ -498,6 +512,8 @@ fpureg,imm32,memam2 \xA0\xC\x00\x2\x0 ARM32,FPA
fpureg,immshifter,memam2 \xA0\xC\x00\x2\x0 ARM32,FPA
[SINcc]
fpureg,fpureg \xA1\1\x11 ARM32,FPA
fpureg,immshifter \xA1\1\x11 ARM32,FPA
[SMLALcc]
reg32,reg32,reg32,reg32 \x85\xFB\xC0\x0\x0 THUMB32,ARMv6T2
@ -1595,6 +1611,8 @@ fpureg,fpureg,fpureg \xA1\0\x6 ARM32,FPA
fpureg,fpureg,immshifter \xA1\0\x6 ARM32,FPA
[RNDcc]
fpureg,fpureg \xA1\1\x7 ARM32,FPA
fpureg,immshifter \xA1\1\x7 ARM32,FPA
[POLcc]
fpureg,fpureg,fpureg \xA1\0\x18 ARM32,FPA
@ -1662,6 +1680,8 @@ fpureg,fpureg,fpureg \xA1\0\x8 ARM32,FPA
fpureg,fpureg,immshifter \xA1\0\x8 ARM32,FPA
[EXPcc]
fpureg,fpureg \xA1\1\xF ARM32,FPA
fpureg,immshifter \xA1\1\xF ARM32,FPA
[FDVcc]
fpureg,fpureg,fpureg \xA1\0\x14 ARM32,FPA

2
compiler/arm/armnop.inc
View File

@ -1,2 +1,2 @@
{ don't edit, this file is generated from armins.dat }
808;
826;

126
compiler/arm/armtab.inc
View File

@ -770,6 +770,90 @@
code : #50#1#111#15#16;
flags : if_arm32 or if_armv4
),
(
opcode : A_CPS;
ops : 1;
optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #143#243#175#129#0;
flags : if_thumb32 or if_armv6t2
),
(
opcode : A_CPS;
ops : 1;
optypes : (ot_immediateshifter,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #70#241#2#0#0;
flags : if_arm32 or if_armv6
),
(
opcode : A_CPSID;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #108#182#112;
flags : if_thumb or if_armv6
),
(
opcode : A_CPSID;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #143#243#175#134#0;
flags : if_thumb32 or if_wide or if_armv6t2
),
(
opcode : A_CPSID;
ops : 2;
optypes : (ot_modeflags,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #143#243#175#135#0;
flags : if_thumb32 or if_wide or if_armv6t2
),
(
opcode : A_CPSID;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #70#241#12#0#0;
flags : if_arm32 or if_armv6
),
(
opcode : A_CPSID;
ops : 2;
optypes : (ot_modeflags,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #70#241#14#0#0;
flags : if_arm32 or if_armv6
),
(
opcode : A_CPSIE;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #108#182#96;
flags : if_thumb or if_armv6
),
(
opcode : A_CPSIE;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #143#243#175#132#0;
flags : if_thumb32 or if_wide or if_armv6t2
),
(
opcode : A_CPSIE;
ops : 2;
optypes : (ot_modeflags,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #143#243#175#133#0;
flags : if_thumb32 or if_wide or if_armv6t2
),
(
opcode : A_CPSIE;
ops : 1;
optypes : (ot_modeflags,ot_none,ot_none,ot_none,ot_none,ot_none);
code : #70#241#8#0#0;
flags : if_arm32 or if_armv6
),
(
opcode : A_CPSIE;
ops : 2;
optypes : (ot_modeflags,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #70#241#10#0#0;
flags : if_arm32 or if_armv6
),
(
opcode : A_EOR;
ops : 2;
@ -1792,6 +1876,20 @@
code : #160#12#0#2#0;
flags : if_arm32 or if_fpa
),
(
opcode : A_SIN;
ops : 2;
optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
code : #161#1#17;
flags : if_arm32 or if_fpa
),
(
opcode : A_SIN;
ops : 2;
optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #161#1#17;
flags : if_arm32 or if_fpa
),
(
opcode : A_SMLAL;
ops : 4;
@ -5355,6 +5453,20 @@
code : #161#0#6;
flags : if_arm32 or if_fpa
),
(
opcode : A_RND;
ops : 2;
optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
code : #161#1#7;
flags : if_arm32 or if_fpa
),
(
opcode : A_RND;
ops : 2;
optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #161#1#7;
flags : if_arm32 or if_fpa
),
(
opcode : A_POL;
ops : 3;
@ -5572,6 +5684,20 @@
code : #161#0#8;
flags : if_arm32 or if_fpa
),
(
opcode : A_EXP;
ops : 2;
optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
code : #161#1#15;
flags : if_arm32 or if_fpa
),
(
opcode : A_EXP;
ops : 2;
optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
code : #161#1#15;
flags : if_arm32 or if_fpa
),
(
opcode : A_FDV;
ops : 3;