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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
This commit is contained in:
mazen
parent
3a78921639
commit
f97aa452bd
@ -1315,7 +1315,6 @@ implementation
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{ move register parameters which aren't regable into memory }
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{ we do this after init_paras because it saves some code in init_paras if parameters are in register }
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{ instead in memory }
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{$IFNDEF SPARC}
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hp:=tparaitem(procinfo.procdef.para.first);
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while assigned(hp) do
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begin
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@ -1353,7 +1352,6 @@ implementation
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end;
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hp:=tparaitem(hp.next);
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end;
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{$ENDIF SPARC}
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end;
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if (not inlined) then
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@ -1848,7 +1846,10 @@ implementation
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end.
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{
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$Log$
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Revision 1.57 2002-11-03 20:22:40 mazen
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Revision 1.58 2002-11-10 19:07:45 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.57 2002/11/03 20:22:40 mazen
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* parameter handling updated
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Revision 1.56 2002/10/16 19:01:43 peter
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@ -31,7 +31,6 @@ uses
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const
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MaxPrefixes=4;
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type
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TOperandOrder=(op_intel,op_att);
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{ alignment for operator }
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tai_align=class(tai_align_abstract)
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reg:tregister;
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@ -46,15 +45,13 @@ type
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constructor op_const(op:tasmop;_op1:aword);
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constructor op_ref(op:tasmop;const _op1:treference);
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constructor op_reg_reg(op:tasmop;_op1,_op2:tregister);
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constructor op_reg_ref(op:tasmop;_op1:tregister;const _op2:treference);
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constructor op_reg_ref(Op:TAsmOp;Reg:TRegister;const Ref:TReference);
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constructor op_reg_const(op:tasmop;_op1:tregister;_op2:aword);
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constructor op_const_reg(op:tasmop;_op1:aword;_op2:tregister);
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constructor op_ref_reg(op:tasmop;const _op1:treference;_op2:tregister);
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{ this is only allowed if _op1 is an int value (_op1^.isintvalue=true) }
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constructor op_ref_ref(op:tasmop;_size:topsize;const _op1,_op2:treference);
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constructor op_reg_reg_reg(op:tasmop;_op1,_op2,_op3:tregister);
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constructor op_reg_const_reg(op:tasmop;_size:topsize;_op1:TRegister;_op2:aWord;_op3:tregister);
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constructor op_reg_ref_reg(op:tasmop;_size:topsize;_op1:tregister;const _op2:treference;_op3:TRegister);
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constructor op_ref_reg(Op:TAsmOp;const Ref:TReference;Reg:TRegister);
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constructor op_ref_ref(op:tasmop;_size:topsize;const _op1,_op2:treference);
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constructor op_reg_reg_reg(op:tasmop;_op1,_op2,_op3:tregister);
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constructor op_reg_const_reg(Op:TAsmOp;SrcReg:TRegister;value:aWord;DstReg:TRegister);
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constructor op_const_ref_reg(op:tasmop;_size:topsize;_op1:aword;const _op2:treference;_op3:tregister);
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constructor op_const_reg_ref(op:tasmop;_size:topsize;_op1:aword;_op2:tregister;const _op3:treference);
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@ -72,7 +69,6 @@ type
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procedure loadcaddr(opidx:longint;aReg:TRegister;cnst:Integer);
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procedure loadraddr(opidx:longint;rg1,rg2:TRegister);
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private
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FOperandOrder:TOperandOrder;
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procedure init(_size:topsize);{this need to be called by all constructor}
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public
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{ the next will reset all instructions that can change in pass 2 }
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@ -80,7 +76,6 @@ type
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procedure ResetPass2;
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function CheckIfValid:boolean;
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function Pass1(offset:longint):longint;virtual;
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procedure SetOperandOrder(order:TOperandOrder);
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private
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{ next fields are filled in pass1, so pass2 is faster }
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insentry : PInsEntry;
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@ -153,10 +148,7 @@ procedure taicpu.changeopsize(siz:topsize);
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end;
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procedure taicpu.init(_size:topsize);
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begin
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{ default order is att }
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FOperandOrder:=op_att;
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{segprefix:=R_NONE;}{This may be only for I386 architecture!}
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opsize:=_size;
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opsize:=_size;
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end;
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constructor taicpu.op_none(op:tasmop);
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begin
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@ -200,13 +192,16 @@ constructor taicpu.op_reg_const(op:tasmop;_op1:tregister; _op2:aword);
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loadreg(0,_op1);
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loadconst(1,_op2);
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end;
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constructor taicpu.op_reg_ref(op:tasmop;_op1:tregister;const _op2:treference);
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constructor taicpu.op_reg_ref(Op:TAsmOp;Reg:TRegister;const Ref:TReference);
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begin
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inherited create(op);
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init(_size);
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ops:=2;
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loadreg(0,_op1);
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loadref(1,_op2);
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if not(Op in [A_STB..A_STDFQ])
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then
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fail;
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inherited Create(Op);
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init(_size);
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ops:=2;
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LoadReg(0,Reg);
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LoadRef(1,Ref);
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end;
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constructor taicpu.op_const_reg(op:tasmop;_op1:aword;_op2:tregister);
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begin
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@ -216,13 +211,16 @@ constructor taicpu.op_const_reg(op:tasmop;_op1:aword;_op2:tregister);
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loadconst(0,_op1);
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loadreg(1,_op2);
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end;
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constructor taicpu.op_ref_reg(op:tasmop;const _op1:treference;_op2:tregister);
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constructor TAiCpu.op_ref_reg(Op:TAsmOp;const Ref:TReference;Reg:TRegister);
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begin
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inherited create(op);
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init(S_SW);
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ops:=2;
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loadref(0,_op1);
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loadreg(1,_op2);
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if not(Op in [A_JMPL,A_FLUSH,A_LDSB..A_LDDC,A_RETT,A_SWAP])
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then
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fail;
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inherited Create(Op);
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Init(S_SW);
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Ops:=2;
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LoadRef(0,Ref);
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LoadReg(1,Reg);
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end;
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constructor taicpu.op_ref_ref(op:tasmop;_size:topsize;const _op1,_op2:treference);
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begin
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@ -241,23 +239,14 @@ constructor taicpu.op_reg_reg_reg(op:tasmop;_op1,_op2,_op3:tregister);
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loadreg(1,_op2);
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loadreg(2,_op3);
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end;
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CONSTRUCTOR taicpu.op_reg_const_reg(op:tasmop;_size:topsize;_op1:TRegister;_op2:aWord;_op3:TRegister);
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BEGIN
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INHERITED create(op);
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init(_size);
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ops:=3;
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LoadReg(0,_op1);
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LoadConst(1,_op2);
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LoadReg(2,_op3);
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END;
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constructor taicpu.op_reg_ref_reg(op:tasmop;_size:topsize;_op1:tregister;const _op2:treference;_op3:tregister);
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constructor taicpu.op_reg_const_reg(op:TAsmOp;SrcReg:TRegister;Value:aWord;DstReg:TRegister);
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begin
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inherited create(op);
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init(_size);
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inherited Create(Op);
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Init(S_W);
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ops:=3;
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LoadReg(0,_op1);
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LoadRef(1,_op2);
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LoadReg(2,_op3);
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LoadReg(0,SrcReg);
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LoadConst(1,Value);
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LoadReg(2,DstReg);
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end;
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constructor taicpu.op_const_ref_reg(op:tasmop;_size:topsize;_op1:aword;const _op2:treference;_op3:tregister);
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begin
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@ -421,18 +410,6 @@ procedure taicpu.Swatoperands;
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end;
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end;
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end;
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procedure taicpu.SetOperandOrder(order:TOperandOrder);
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begin
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if FOperandOrder<>order then
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begin
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Swatoperands;
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FOperandOrder:=order;
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end;
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end;
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{ This check must be done with the operand in ATT order
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i.e.after swapping in the intel reader
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but before swapping in the NASM and TASM writers PM }
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@ -711,8 +688,6 @@ begin
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optimize }
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if (Insentry=nil) or ((InsEntry^.flags and IF_PASS2)<>0) then
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begin
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{ We need intel style operands }
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SetOperandOrder(op_intel);
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{ create the .ot fields }
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create_ot;
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{ set the file postion }
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@ -1138,7 +1113,10 @@ procedure InitAsm;
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end.
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{
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$Log$
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Revision 1.11 2002-11-06 11:31:24 mazen
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Revision 1.12 2002-11-10 19:07:46 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.11 2002/11/06 11:31:24 mazen
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* op_reg_reg_reg don't need any more a TOpSize parameter
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Revision 1.10 2002/11/05 16:15:00 mazen
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@ -122,7 +122,7 @@ procedure emit_reg_reg(i:tasmop;s:topsize;reg1,reg2:tregister);
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end;
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procedure emit_const_reg_reg(i:tasmop;s:topsize;c:longint;reg1,reg2:tregister);
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begin
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exprasmList.concat(Taicpu.Op_reg_const_reg(i,S_L,reg1,c,reg2));
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exprasmList.concat(Taicpu.Op_reg_const_reg(i,reg1,c,reg2));
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end;
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procedure emit_reg_reg_reg(i:tasmop;s:topsize;reg1,reg2,reg3:tregister);
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begin
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@ -135,7 +135,10 @@ procedure emit_sym(i:tasmop;s:topsize;op:tasmsymbol);
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end.
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{
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$Log$
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Revision 1.4 2002-11-06 11:31:24 mazen
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Revision 1.5 2002-11-10 19:07:46 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.4 2002/11/06 11:31:24 mazen
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* op_reg_reg_reg don't need any more a TOpSize parameter
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Revision 1.3 2002/10/22 13:43:01 mazen
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@ -28,7 +28,6 @@ USES
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node,symconst;
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TYPE
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tcgSPARC=CLASS(tcg)
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FreeParamRegSet:TRegisterSet;
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{This method is used to pass a parameter, which is located in a register, to a
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routine. It should give the parameter to the routine, as required by the
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specific processor ABI. It is overriden for each CPU target.
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@ -212,7 +211,7 @@ procedure tcgSPARC.a_load_const_reg(list:TAasmOutput;size:TCGSize;a:aword;reg:TR
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WITH List DO
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IF a<>0
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THEN{R_G0 is usually set to zero, so we use it}
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Concat(taicpu.op_reg_const_reg(A_OR,TCGSize2OpSize[size],R_G0,a,reg))
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Concat(taicpu.op_reg_const_reg(A_OR,R_G0,a,reg))
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ELSE{The is no A_MOV in sparc, that's why we use A_OR with help of R_G0}
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Concat(taicpu.op_reg_reg_reg(A_OR,R_G0,R_G0,reg));
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END;
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@ -668,7 +667,7 @@ procedure tcgSPARC.a_op_const_reg(list:TAasmOutput;Op:TOpCG;a:AWord;reg:TRegiste
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ispowerof2(a,power) then
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{ can be done with a shift }
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inherited a_op_const_reg_reg(list,op,size,a,src,dst);
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list.concat(taicpu.op_reg_const_reg(A_SMUL,S_SW,src,a,dst));
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list.concat(taicpu.op_reg_const_reg(A_SMUL,src,a,dst));
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end;
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OP_ADD, OP_SUB:
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if (a = 0) then
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@ -822,7 +821,7 @@ stack frame. In the "SAVE %i6,size,%i6" the first %i6 is related to the state
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before execution of the SAVE instrucion so it is the caller %i6, when the %i6
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after execution of that instruction is the called function stack pointer}
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with list do
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concat(Taicpu.Op_reg_const_reg(A_SAVE,S_SW,Stack_Pointer_Reg,LocalSize,Stack_Pointer_Reg));
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concat(Taicpu.Op_reg_const_reg(A_SAVE,Stack_Pointer_Reg,LocalSize,Stack_Pointer_Reg));
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end;
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procedure tcgSPARC.g_restore_frame_pointer(list:TAasmOutput);
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begin
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@ -847,7 +846,7 @@ If no inversion we can use just
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concat(Taicpu.Op_caddr_reg(A_JMPL,R_I7,8,R_G0));
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{We use trivial restore in the delay slot of the JMPL instruction, as we
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already set result onto %i0}
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concat(Taicpu.Op_reg_const_reg(A_RESTORE,S_SW,R_G0,0,R_G0));
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concat(Taicpu.Op_reg_const_reg(A_RESTORE,R_G0,0,R_G0));
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end
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end;
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procedure tcgSPARC.a_loadaddr_ref_reg(list:TAasmOutput;CONST ref:TReference;r:tregister);
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@ -1053,8 +1052,8 @@ procedure TCgSparc.g_concatcopy(list:taasmoutput;const source,dest:treference;le
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{ easy to notice in the generated assembler }
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inc(dst.offset,8);
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inc(src.offset,8);
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list.concat(taicpu.op_reg_const_reg(A_SUB,S_SW,src.base,8,src.base));
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list.concat(taicpu.op_reg_const_reg(A_SUB,S_SW,dst.base,8,dst.base));
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list.concat(taicpu.op_reg_const_reg(A_SUB,src.base,8,src.base));
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list.concat(taicpu.op_reg_const_reg(A_SUB,dst.base,8,dst.base));
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countreg := get_scratch_reg_int(list);
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a_load_const_reg(list,OS_32,count,countreg);
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{ explicitely allocate R_O0 since it can be used safely here }
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@ -1062,7 +1061,7 @@ procedure TCgSparc.g_concatcopy(list:taasmoutput;const source,dest:treference;le
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a_reg_alloc(list,R_F0);
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objectlibrary.getlabel(lab);
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a_label(list, lab);
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list.concat(taicpu.op_reg_const_reg(A_SUB,S_SW,countreg,1,countreg));
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list.concat(taicpu.op_reg_const_reg(A_SUB,countreg,1,countreg));
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list.concat(taicpu.op_reg_ref(A_LDF,R_F0,src));
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list.concat(taicpu.op_reg_ref(A_STD,R_F0,dst));
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//a_jmp(list,A_BC,C_NE,0,lab);
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@ -1254,7 +1253,10 @@ BEGIN
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END.
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{
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$Log$
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Revision 1.22 2002-11-06 11:31:24 mazen
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Revision 1.23 2002-11-10 19:07:46 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.22 2002/11/06 11:31:24 mazen
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* op_reg_reg_reg don't need any more a TOpSize parameter
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Revision 1.21 2002/11/05 16:15:00 mazen
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@ -160,7 +160,6 @@ procedure TGasSPARC.WriteInstruction(hp:Tai);
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if hp.typ<>ait_instruction
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then
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Exit;
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taicpu(hp).SetOperandOrder(op_att);
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op:=taicpu(hp).opcode;
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{call maybe not translated to call}
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s:=#9+std_op2str[op]+cond2str[taicpu(hp).condition];
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@ -210,7 +209,10 @@ initialization
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end.
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{
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$Log$
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Revision 1.8 2002-10-25 19:37:53 mazen
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Revision 1.9 2002-11-10 19:07:46 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.8 2002/10/25 19:37:53 mazen
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* bug of references name missing last character fixed
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Revision 1.7 2002/10/20 19:01:38 mazen
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@ -72,9 +72,9 @@ procedure TSparcProcInfo.after_pass1;
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else
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procdef.localst.address_fixup:=6*4+(16+1)*4;
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procinfo.firsttemp_offset:=procdef.localst.address_fixup+procdef.localst.datasize;
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WriteLn('Parameter copies start at: %i6-'+tostr(procdef.parast.address_fixup));
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WriteLn('Locals start at: %o6-'+tostr(procdef.localst.address_fixup));
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WriteLn('Temp. space start: %o6-'+tostr(procinfo.firsttemp_offset));
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WriteLn('Parameter copies start at: %i6+'+tostr(procdef.parast.address_fixup));
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WriteLn('Locals start at: %o6+'+tostr(procdef.localst.address_fixup));
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WriteLn('Temp. space start: %o6+'+tostr(procinfo.firsttemp_offset));
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tg.firsttemp:=procinfo.firsttemp_offset;
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tg.lasttemp:=procinfo.firsttemp_offset;
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end;
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@ -83,7 +83,10 @@ begin
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end.
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{
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$Log$
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Revision 1.5 2002-11-03 20:22:40 mazen
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Revision 1.6 2002-11-10 19:07:46 mazen
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* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
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Revision 1.5 2002/11/03 20:22:40 mazen
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* parameter handling updated
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Revision 1.4 2002/10/20 19:01:38 mazen
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@ -122,7 +122,7 @@ procedure TSparcAddNode.left_must_be_reg(OpSize:TOpSize;NoSwap:Boolean);
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begin
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{maybe we can reuse a constant register when the operation is a comparison that
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doesn't change the value of the register}
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location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],(nodetype IN [ltn,lten,gtn,gten,equaln,unequaln]));
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location_force_reg(exprasmlist,left.location,opsize_2_cgsize[opsize],(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
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end;
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end;
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procedure TSparcAddNode.emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extra_not,mboverflow:Boolean);
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@ -181,9 +181,10 @@ procedure TSparcAddNode.emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extr
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end
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ELSE IF(op=A_ADD)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
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THEN
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begin
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emit_reg(A_INC,opsize,left.location.register);
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end
|
||||
with ExprAsmList,left.location do
|
||||
begin
|
||||
concat(TAiCpu.op_reg_const_reg(A_ADD,register,1,register));
|
||||
end
|
||||
ELSE IF(op=A_SUB)AND(right.location.loc=LOC_CONSTANT)AND(right.location.value=1)AND NOT(cs_check_overflow in aktlocalswitches)
|
||||
THEN
|
||||
begin
|
||||
@ -236,14 +237,17 @@ procedure TSparcAddNode.emit_generic_code(op:TAsmOp;OpSize:TOpSize;unsigned,extr
|
||||
procedure TSparcAddNode.emit_op_right_left(op:TAsmOp);
|
||||
begin
|
||||
{left must be a register}
|
||||
with exprasmlist do
|
||||
case right.location.loc of
|
||||
with left,location,exprasmlist do
|
||||
case Right.Location.Loc of
|
||||
LOC_REGISTER,LOC_CREGISTER:
|
||||
concat(taicpu.op_reg_reg_reg(op,right.location.register,left.location.register,left.location.register));
|
||||
concat(taicpu.op_reg_reg_reg(op,Register,Right.Location.register,register));
|
||||
LOC_REFERENCE,LOC_CREFERENCE :
|
||||
concat(taicpu.op_reg_ref_reg(op,S_W,left.location.register,right.location.reference,left.location.register));
|
||||
begin
|
||||
location_force_reg(exprasmlist,Right.Location,OS_32,(nodetype in [ltn,lten,gtn,gten,equaln,unequaln]));
|
||||
concat(taicpu.op_reg_reg_reg(op,register,Right.Location.register,register));
|
||||
end;
|
||||
LOC_CONSTANT:
|
||||
concat(taicpu.op_reg_const_reg(op,S_W,left.location.register,right.location.value,left.location.register));
|
||||
concat(taicpu.op_reg_const_reg(op,register,Right.Location.value,register));
|
||||
else
|
||||
InternalError(200203232);
|
||||
end;
|
||||
@ -404,7 +408,10 @@ begin
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.8 2002-11-06 15:34:00 mazen
|
||||
Revision 1.9 2002-11-10 19:07:46 mazen
|
||||
* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
|
||||
|
||||
Revision 1.8 2002/11/06 15:34:00 mazen
|
||||
*** empty log message ***
|
||||
|
||||
Revision 1.7 2002/11/06 11:31:24 mazen
|
||||
|
||||
@ -236,13 +236,13 @@ implementation
|
||||
internalerror(200110012);
|
||||
end;
|
||||
tempreg := cg.get_scratch_reg_int(exprasmlist);
|
||||
{$WARNING FIXME what reallty should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_OR,S_L,tempreg,$4330,tempreg));
|
||||
{$WARNING FIXME what really should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_OR,tempreg,$4330,tempreg));
|
||||
cg.a_load_reg_ref(exprasmlist,OS_32,tempreg,ref);
|
||||
cg.free_scratch_reg(exprasmlist,tempreg);
|
||||
if signed then
|
||||
{$WARNING FIXME what reallty should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_XOR,S_L,leftreg,$8000,valuereg));
|
||||
{$WARNING FIXME what really should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_XOR,leftreg,$8000,valuereg));
|
||||
inc(ref.offset,4);
|
||||
cg.a_load_reg_ref(exprasmlist,OS_32,valuereg,ref);
|
||||
dec(ref.offset,4);
|
||||
@ -262,7 +262,7 @@ implementation
|
||||
tempconst.free;
|
||||
|
||||
location.register := rg.getregisterfpu(exprasmlist);
|
||||
{$WARNING FIXME what reallty should be done?}
|
||||
{$WARNING FIXME what really should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_ref(A_LD,location.register,ref));
|
||||
|
||||
tg.ungetiftemp(exprasmlist,ref);
|
||||
@ -273,7 +273,7 @@ implementation
|
||||
|
||||
{ work around bug in some PowerPC processors }
|
||||
if (tfloatdef(resulttype.def).typ = s32real) then
|
||||
{$WARNING FIXME what reallty should be done?}
|
||||
{$WARNING FIXME what really should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_reg(A_ADD,location.register,location.register));
|
||||
end;
|
||||
|
||||
@ -285,7 +285,7 @@ implementation
|
||||
{ properly converted to singles }
|
||||
if (tfloatdef(left.resulttype.def).typ = s64real) and
|
||||
(tfloatdef(resulttype.def).typ = s32real) then
|
||||
{$WARNING FIXME what reallty should be done?}
|
||||
{$WARNING FIXME what really should be done?}
|
||||
exprasmlist.concat(taicpu.op_reg_reg(A_ADD,location.register,location.register));
|
||||
end;
|
||||
|
||||
@ -323,7 +323,7 @@ implementation
|
||||
else
|
||||
hreg2 := left.location.register;
|
||||
hreg1 := rg.getregisterint(exprasmlist);
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_SUB,S_L,hreg1,1,
|
||||
exprasmlist.concat(taicpu.op_reg_const_reg(A_SUB,hreg1,1,
|
||||
hreg2));
|
||||
exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUB,hreg1,hreg1,hreg2));
|
||||
rg.ungetregister(exprasmlist,hreg2);
|
||||
@ -420,7 +420,10 @@ begin
|
||||
end.
|
||||
{
|
||||
$Log$
|
||||
Revision 1.6 2002-11-06 11:31:24 mazen
|
||||
Revision 1.7 2002-11-10 19:07:46 mazen
|
||||
* SPARC calling mechanism almost OK (as in GCC./mppcsparc )
|
||||
|
||||
Revision 1.6 2002/11/06 11:31:24 mazen
|
||||
* op_reg_reg_reg don't need any more a TOpSize parameter
|
||||
|
||||
Revision 1.5 2002/10/22 13:43:01 mazen
|
||||
|
||||
Loading…
Reference in New Issue
Block a user