mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-06 07:47:59 +02:00
+ Xtensa: hard float support, i.e. make use of floating point extension if available
git-svn-id: trunk@44539 -
This commit is contained in:
florian
parent
ba3de67f3b
commit
fa4cbc89a5
@ -372,7 +372,8 @@ interface
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implementation
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uses
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verbose,cutils;
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verbose,cutils,
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cpuinfo;
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{ returns true, if def uses FPU }
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function is_fpu(def : tdef) : boolean;
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@ -1518,7 +1519,12 @@ implementation
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objectdef :
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result:=int_cgsize(def.size);
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floatdef:
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if cs_fp_emulation in current_settings.moduleswitches then
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if (cs_fp_emulation in current_settings.moduleswitches) or
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{$ifdef xtensa}
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not(tfloatdef(def).floattype=s32real) or
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not(FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype])
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{$endif xtensa}
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then
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result:=int_cgsize(def.size)
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else
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result:=tfloat2tcgsize[tfloatdef(def).floattype];
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@ -751,6 +751,10 @@ implementation
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and (use_vectorfpu(left.resultdef) and
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use_vectorfpu(right.resultdef) and
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(tfloatdef(left.resultdef).floattype=tfloatdef(right.resultdef).floattype))
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{$endif arm}
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{$ifdef xtensa}
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and not((FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) xor
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(FPUXTENSA_DOUBLE in fpu_capabilities[current_settings.fputype]))
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{$endif}
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then
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begin
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@ -2357,7 +2357,11 @@ implementation
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{$ifdef x86}
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result:=use_vectorfpu(self);
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{$else x86}
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result:=(typ=floatdef) and not(cs_fp_emulation in current_settings.moduleswitches);
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result:=(typ=floatdef) and not(cs_fp_emulation in current_settings.moduleswitches) and
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{$ifdef xtensa}
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(FPUXTENSA_SINGLE in fpu_capabilities[init_settings.fputype]) and (tfloatdef(self).floattype=s32real)
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{$endif xtensa}
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;
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{$endif x86}
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end;
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@ -73,6 +73,10 @@ interface
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procedure g_concatcopy(list : TAsmList; const source,dest : treference; len : tcgint);override;
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procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister);override;
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procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister);override;
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procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
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procedure maybeadjustresult(list: TAsmList; op: TOpCg; size: tcgsize; dst: tregister);
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end;
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@ -945,6 +949,49 @@ implementation
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end;
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procedure tcgcpu.a_loadfpu_reg_reg(list: TAsmList; fromsize,tosize: tcgsize; reg1, reg2: tregister);
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begin
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if not(fromsize in [OS_32,OS_F32]) then
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InternalError(2020032603);
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list.concat(taicpu.op_reg_reg(A_MOV_S,reg2,reg1));
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end;
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procedure tcgcpu.a_loadfpu_ref_reg(list: TAsmList; fromsize,tosize: tcgsize; const ref: treference; reg: tregister);
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var
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href: treference;
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begin
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if not(fromsize in [OS_32,OS_F32]) then
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InternalError(2020032602);
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href:=ref;
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if assigned(href.symbol) or
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(href.index<>NR_NO) or
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(((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) then
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fixref(list,href);
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list.concat(taicpu.op_reg_ref(A_LSI,reg,href));
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if fromsize<>tosize then
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a_loadfpu_reg_reg(list,fromsize,tosize,reg,reg);
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end;
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procedure tcgcpu.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
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var
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href: treference;
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begin
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if not(fromsize in [OS_32,OS_F32]) then
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InternalError(2020032604);
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href:=ref;
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if assigned(href.symbol) or
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(href.index<>NR_NO) or
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(((href.offset<0) or (href.offset>1020) or (href.offset mod 4<>0))) then
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fixref(list,href);
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list.concat(taicpu.op_reg_ref(A_SSI,reg,href));
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end;
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procedure tcgcpu.maybeadjustresult(list : TAsmList; op : TOpCg; size : tcgsize; dst : tregister);
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const
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overflowops = [OP_MUL,OP_SHL,OP_ADD,OP_SUB,OP_NEG];
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@ -45,7 +45,8 @@ Type
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tfputype =
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(fpu_none,
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fpu_soft,
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fpu_libgcc
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fpu_libgcc,
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fpu_hard
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);
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Type
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@ -97,7 +98,8 @@ Const
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fputypestr : array[tfputype] of string[10] = (
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'NONE',
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'SOFT',
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'LIBGCC'
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'LIBGCC',
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'HARD'
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);
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@ -109,10 +111,10 @@ Const
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; abi: abi_default; flashbase:0),
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(controllertypestr:'ESP8266'; controllerunitstr:'ESP8266'; cputype:cpu_lx106; fputype:fpu_none; abi: abi_xtensa_call0; { flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024 }),
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(controllertypestr:'ESP32'; controllerunitstr:'ESP32'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:2*1024*1024),
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(controllertypestr:'ESP32_D0WD'; controllerunitstr:'ESP32_D0WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
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(controllertypestr:'ESP32_D2WD'; controllerunitstr:'ESP32_D2WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
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(controllertypestr:'ESP32_S0WD'; controllerunitstr:'ESP32_S0WD'; cputype:cpu_lx6; fputype:fpu_none; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024)
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(controllertypestr:'ESP32'; controllerunitstr:'ESP32'; cputype:cpu_lx6; fputype:fpu_hard; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:2*1024*1024),
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(controllertypestr:'ESP32_D0WD'; controllerunitstr:'ESP32_D0WD'; cputype:cpu_lx6; fputype:fpu_hard; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
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(controllertypestr:'ESP32_D2WD'; controllerunitstr:'ESP32_D2WD'; cputype:cpu_lx6; fputype:fpu_hard; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024),
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(controllertypestr:'ESP32_S0WD'; controllerunitstr:'ESP32_S0WD'; cputype:cpu_lx6; fputype:fpu_hard; abi: abi_xtensa_windowed; flashbase:$40000000; flashsize:448*1024; srambase:$40070000; sramsize: 520*1024)
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);
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{ Supported optimizations, only used for information }
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@ -138,7 +140,8 @@ Const
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tfpuflags =
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(
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FPUXTENSA_DUMMY
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FPUXTENSA_SINGLE, { FPU has single support }
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FPUXTENSA_DOUBLE { FPU has double support, this is a dummy so far for easier checking what code to generate }
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);
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const
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@ -153,7 +156,8 @@ Const
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(
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{ fpu_none } [],
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{ fpu_soft } [],
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{ fpu_libgcc } []
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{ fpu_libgcc } [],
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{ fpu_hard } [FPUXTENSA_SINGLE]
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);
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Implementation
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@ -30,11 +30,16 @@ interface
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type
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TCPUAddNode = class(tcgaddnode)
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private
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procedure pass_left_and_right;
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protected
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function pass_1 : tnode;override;
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function first_addfloat: tnode;override;
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procedure second_cmpordinal;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_cmpfloat;override;
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procedure second_addfloat;override;
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procedure second_cmp;
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end;
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@ -176,6 +181,127 @@ interface
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second_cmp;
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end;
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procedure TCPUAddNode.pass_left_and_right;
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begin
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{ calculate the operator which is more difficult }
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firstcomplex(self);
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{ in case of constant put it to the left }
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if (left.nodetype=ordconstn) then
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swapleftright;
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secondpass(left);
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secondpass(right);
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end;
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function TCPUAddNode.first_addfloat: tnode;
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begin
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result := nil;
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if (FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) and
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(tfloatdef(left.resultdef).floattype=s32real) and (nodetype<>slashn) then
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begin
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if nodetype in [equaln,unequaln,lten,ltn,gten,gtn] then
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expectloc:=LOC_FLAGS
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else
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expectloc:=LOC_FPUREGISTER;
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end
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else
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result:=first_addfloat_soft;
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end;
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procedure TCPUAddNode.second_addfloat;
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var
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op : TAsmOp;
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cmpop,
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singleprec , inv: boolean;
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begin
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pass_left_and_right;
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if (nf_swapped in flags) then
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swapleftright;
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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cmpop:=false;
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inv:=false;
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case nodetype of
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addn :
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op:=A_ADD_S;
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muln :
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op:=A_MUL_S;
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subn :
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op:=A_SUB_S;
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unequaln,
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equaln:
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begin
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op:=A_OEQ_S;
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cmpop:=true;
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end;
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ltn:
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begin
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op:=A_OLT_S;
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cmpop:=true;
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end;
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lten:
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begin
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op:=A_OLE_S;
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cmpop:=true;
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end;
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gtn:
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begin
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op:=A_OLT_S;
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swapleftright;
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cmpop:=true;
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end;
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gten:
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begin
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op:=A_OLE_S;
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swapleftright;
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cmpop:=true;
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end;
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else
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internalerror(2020032601);
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end;
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{ initialize de result }
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if cmpop then
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begin
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags.register:=NR_B0;
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location.resflags.flag:=F_NZ;
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end
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else
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begin
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
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end;
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{ emit the actual operation }
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if cmpop then
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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if inv then
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location.resflags.flag:=F_Z;
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end
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else
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,location.register,left.location.register,right.location.register));
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cg.maybe_check_for_fpu_exception(current_asmdata.CurrAsmList);
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end;
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end;
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procedure TCPUAddNode.second_cmpfloat;
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begin
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second_addfloat;
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end;
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begin
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caddnode:=tcpuaddnode;
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end.
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@ -30,29 +30,9 @@ interface
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type
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tcputypeconvnode = class(tcgtypeconvnode)
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protected
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// function first_int_to_real: tnode;override;
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// function first_real_to_real: tnode; override;
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{ procedure second_int_to_int;override; }
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{ procedure second_string_to_string;override; }
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{ procedure second_cstring_to_pchar;override; }
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{ procedure second_string_to_chararray;override; }
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{ procedure second_array_to_pointer;override; }
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// function first_int_to_real: tnode; override;
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{ procedure second_pointer_to_array;override; }
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{ procedure second_chararray_to_string;override; }
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{ procedure second_char_to_string;override; }
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// procedure second_int_to_real;override;
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// procedure second_real_to_real;override;
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{ procedure second_cord_to_pointer;override; }
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{ procedure second_proc_to_procvar;override; }
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{ procedure second_bool_to_int;override; }
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procedure second_int_to_bool;override;
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{ procedure second_load_smallset;override; }
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{ procedure second_ansistring_to_pchar;override; }
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{ procedure second_pchar_to_string;override; }
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{ procedure second_class_to_intf;override; }
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{ procedure second_char_to_char;override; }
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protected
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function first_real_to_real: tnode;override;
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procedure second_int_to_bool;override;
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end;
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implementation
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@ -70,6 +50,51 @@ implementation
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tcputypeconvnode
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*****************************************************************************}
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function tcputypeconvnode.first_real_to_real: tnode;
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begin
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if (FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) and
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not(FPUXTENSA_DOUBLE in fpu_capabilities[current_settings.fputype]) then
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begin
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case tfloatdef(left.resultdef).floattype of
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s32real:
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case tfloatdef(resultdef).floattype of
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s64real:
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result:=ctypeconvnode.create_explicit(ccallnode.createintern('float32_to_float64',ccallparanode.create(
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ctypeconvnode.create_internal(left,search_system_type('FLOAT32REC').typedef),nil)),resultdef);
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s32real:
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begin
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result:=left;
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left:=nil;
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end;
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else
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internalerror(200610151);
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end;
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s64real:
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case tfloatdef(resultdef).floattype of
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s32real:
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result:=ctypeconvnode.create_explicit(ccallnode.createintern('float64_to_float32',ccallparanode.create(
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ctypeconvnode.create_internal(left,search_system_type('FLOAT64').typedef),nil)),resultdef);
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s64real:
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begin
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result:=left;
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left:=nil;
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end;
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else
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internalerror(200610152);
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end;
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else
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internalerror(200610153);
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end;
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left:=nil;
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firstpass(result);
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exit;
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end
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else
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Result := inherited first_real_to_real;
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end;
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procedure tcputypeconvnode.second_int_to_bool;
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var
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hreg1, onereg: tregister;
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@ -121,25 +121,40 @@ implementation
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procedure tcpuunaryminusnode.second_float;
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begin
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secondpass(left);
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case current_settings.fputype of
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fpu_soft:
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begin
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if (current_settings.fputype=fpu_soft) or (tfloatdef(left.resultdef).floattype<>s32real) or
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not(FPUXTENSA_SINGLE in fpu_capabilities[current_settings.fputype]) then
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begin
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if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,left.resultdef,false);
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location:=left.location;
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case location.size of
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OS_32:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.register);
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OS_64:
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),location.registerhi);
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else
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internalerror(2014033101);
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end;
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end
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else
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internalerror(2009112602);
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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if location.size in [OS_64,OS_S64,OS_F64] then
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begin
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location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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end
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else
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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case location.size of
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OS_32:
|
||||
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),left.location.register,location.register);
|
||||
OS_64:
|
||||
cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_XOR,OS_32,tcgint($80000000),left.location.registerhi,location.registerhi);
|
||||
else
|
||||
internalerror(2014033101);
|
||||
end;
|
||||
end
|
||||
else
|
||||
begin
|
||||
if not(left.location.loc in [LOC_CFPUREGISTER,LOC_FPUREGISTER]) then
|
||||
hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,false);
|
||||
location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
|
||||
location.register:=cg.getfpuregister(current_asmdata.CurrAsmList,location.size);
|
||||
current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_NEG_S,location.register,left.location.register));
|
||||
end;
|
||||
end;
|
||||
|
||||
|
||||
procedure tcpushlshrnode.second_64bit;
|
||||
var
|
||||
v : TConstExprInt;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user