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* In ARM scheduler move all needed additional items with an instruction:

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- all reg allocs and PIC labeels before the instruction;
  - all reg deallocs and reg syncs after the instruction.

  It fixes bug #31135.

git-svn-id: trunk@35545 -
This commit is contained in:
yury 2017-03-09 12:26:02 +00:00
parent 94b8beb3c2
commit fe0e30030f
1 changed files with 5 additions and 3 deletions
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8
compiler/arm/aoptcpu.pas
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@ -2574,13 +2574,14 @@ Implementation
hp3:=tai(p.Previous); hp3:=tai(p.Previous);
hp5:=tai(p.next); hp5:=tai(p.next);
asml.Remove(p); asml.Remove(p);
{ if there is a reg. dealloc instruction or address labels (e.g. for GOT-less PIC) { if there is a reg. alloc/dealloc/sync instructions or address labels (e.g. for GOT-less PIC)
associated with p, move it together with p } associated with p, move it together with p }
{ before the instruction? } { before the instruction? }
{ find reg allocs and PIC labels }
while assigned(hp3) and (hp3.typ<>ait_instruction) do while assigned(hp3) and (hp3.typ<>ait_instruction) do
begin begin
if ( (hp3.typ=ait_regalloc) and (tai_regalloc(hp3).ratype in [ra_dealloc]) and if ( (hp3.typ=ait_regalloc) and (tai_regalloc(hp3).ratype in [ra_alloc]) and
RegInInstruction(tai_regalloc(hp3).reg,p) ) RegInInstruction(tai_regalloc(hp3).reg,p) )
or ( (hp3.typ=ait_label) and (tai_label(hp3).labsym.typ=AT_ADDR) ) or ( (hp3.typ=ait_label) and (tai_label(hp3).labsym.typ=AT_ADDR) )
then then
@ -2598,9 +2599,10 @@ Implementation
SwapRegLive(taicpu(p),taicpu(hp1)); SwapRegLive(taicpu(p),taicpu(hp1));
{ after the instruction? } { after the instruction? }
{ find reg deallocs and reg syncs }
while assigned(hp5) and (hp5.typ<>ait_instruction) do while assigned(hp5) and (hp5.typ<>ait_instruction) do
begin begin
if (hp5.typ=ait_regalloc) and (tai_regalloc(hp5).ratype in [ra_dealloc]) and if (hp5.typ=ait_regalloc) and (tai_regalloc(hp5).ratype in [ra_dealloc, ra_sync]) and
RegInInstruction(tai_regalloc(hp5).reg,p) then RegInInstruction(tai_regalloc(hp5).reg,p) then
begin begin
hp4:=hp5; hp4:=hp5;