From fecd25bac187d7df0846f58ab719fa2aafede2bd Mon Sep 17 00:00:00 2001
From: florian <florian@freepascal.org>
Date: Fri, 21 Feb 2025 22:47:44 +0100
Subject: [PATCH]   * fix typo   * properly pass zba, zbb, zbs to march

---
 compiler/riscv/agrvgas.pas | 6 +++---
 compiler/riscv/nrvutil.pas | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/compiler/riscv/agrvgas.pas b/compiler/riscv/agrvgas.pas
index c2328f0df7..fdada98b17 100644
--- a/compiler/riscv/agrvgas.pas
+++ b/compiler/riscv/agrvgas.pas
@@ -231,14 +231,14 @@ unit agrvgas;
 
     function TRVGNUAssembler.MakeCmdLine: TCmdStr;
       const
-        arch_str: array[boolean,tcputype] of string[10] = (
+        arch_str: array[boolean,tcputype] of string[18] = (
 {$ifdef RISCV32}
           ('','rv32imac','rv32ima','rv32im','rv32i','rv32e','rv32imc','rv32imafdc','rv32imafd','rv32ec','rv32gc'),
           ('','rv32imafdc','rv32imafd','rv32imfd','rv32ifd','rv32efd','rv32imcfd','rv32imafdc','rv32imafd','rv32ecfd','rv32gc')
 {$endif RISCV32}
 {$ifdef RISCV64}
-          ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gcb'),
-          ('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc','rv64gcb')
+          ('','rv64imac','rv64ima','rv64im','rv64i','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs'),
+          ('','rv64imafdc','rv64imafd','rv64imfd','rv64ifd','rv64imafdc','rv64imafd','rv64gc','rv64gc_zba_zbb_zbs')
 {$endif RISCV64}
         );
       begin
diff --git a/compiler/riscv/nrvutil.pas b/compiler/riscv/nrvutil.pas
index 27a2b3bcca..788d06e178 100644
--- a/compiler/riscv/nrvutil.pas
+++ b/compiler/riscv/nrvutil.pas
@@ -90,7 +90,7 @@ implementation
           if CPURV_HAS_ZICOND in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zicond1p0';
           if CPURV_HAS_CSR_INSTRUCTIONS in cpu_capabilities[current_settings.cputype] then
-            attr_arch:=attr_arch+'_zicrs2p0';
+            attr_arch:=attr_arch+'_zicsr2p0';
           if CPURV_HAS_FETCH_FENCE in cpu_capabilities[current_settings.cputype] then
             attr_arch:=attr_arch+'_zifencei2p0';
           if CPURV_HAS_ZMMUL in cpu_capabilities[current_settings.cputype] then