From ff3b4adc2773934710b014df680d96897948118d Mon Sep 17 00:00:00 2001 From: florian Date: Tue, 30 Jan 2024 22:55:42 +0100 Subject: [PATCH] + more CPU and FPU flags added --- compiler/i386/cpuinfo.pas | 10 +++++++++- compiler/x86_64/cpuinfo.pas | 11 ++++++++++- 2 files changed, 19 insertions(+), 2 deletions(-) diff --git a/compiler/i386/cpuinfo.pas b/compiler/i386/cpuinfo.pas index c879d75940..66ee4ccb63 100644 --- a/compiler/i386/cpuinfo.pas +++ b/compiler/i386/cpuinfo.pas @@ -190,12 +190,18 @@ type CPUX86_HAS_CMOV, { CMOVcc instructions are available } CPUX86_HAS_SSEUNIT, { SSE instructions are available } CPUX86_HAS_SSE2, { SSE2 instructions are available } + CPUX86_HAS_SSE4_1, { SSE 4.1 instructions are available } + CPUX86_HAS_SSE4_2, { SSE 4.2 instructions are available } + CPUX86_HAS_SSSE3, { SSSE3 instructions are available } CPUX86_HAS_BMI1, { BMI1 instructions are available } CPUX86_HAS_BMI2, { BMI2 instructions are available } + CPUX86_HAS_CMPXCHG16B, { CMPXCHG16B is available (not on i386, only for less ifdefs in the compiler } + CPUX86_HAS_LAHF_SAHF, { LAHF/SAHF is available } CPUX86_HAS_POPCNT, { POPCNT is available } CPUX86_HAS_LZCNT, { LZCNT is available } CPUX86_HAS_MOVBE, { MOVBE is available } - CPUX86_HAS_BSWAP { BSWAP is available } + CPUX86_HAS_BSWAP, { BSWAP is available } + CPUX86_HAS_OSXSAVE { XGETBV is available } ); tfpuflags = @@ -204,6 +210,8 @@ type FPUX86_HAS_FMA4, FPUX86_HAS_AVX2, FPUX86_HAS_AVX512F, + FPUX86_HAS_AVX512BW, + FPUX86_HAS_AVX512CD, FPUX86_HAS_AVX512VL, FPUX86_HAS_AVX512DQ ); diff --git a/compiler/x86_64/cpuinfo.pas b/compiler/x86_64/cpuinfo.pas index d035f74383..f11b2a6a85 100644 --- a/compiler/x86_64/cpuinfo.pas +++ b/compiler/x86_64/cpuinfo.pas @@ -192,21 +192,30 @@ type CPUX86_HAS_CMOV, { CMOVcc instructions are available } CPUX86_HAS_SSEUNIT, { SSE instructions are available } CPUX86_HAS_SSE2, { SSE2 instructions are available } + CPUX86_HAS_SSE4_1, { SSE 4.1 instructions are available } + CPUX86_HAS_SSE4_2, { SSE 4.2 instructions are available } + CPUX86_HAS_SSSE3, { SSSE3 instructions are available } CPUX86_HAS_BMI1, { BMI1 instructions are available } CPUX86_HAS_BMI2, { BMI2 instructions are available } + CPUX86_HAS_CMPXCHG16B, { CMPXCHG16B is available } + CPUX86_HAS_LAHF_SAHF, { LAHF/SAHF is available } CPUX86_HAS_POPCNT, { POPCNT is available } CPUX86_HAS_LZCNT, { LZCNT is available } CPUX86_HAS_MOVBE, { MOVBE is available } - CPUX86_HAS_BSWAP { BSWAP is available } + CPUX86_HAS_BSWAP, { BSWAP is available } + CPUX86_HAS_OSXSAVE { XGETBV is available } ); tfpuflags = (FPUX86_HAS_AVXUNIT, FPUX86_HAS_FMA, FPUX86_HAS_FMA4, + FPUX86_HAS_F16C, FPUX86_HAS_AVX2, FPUX86_HAS_32MMREGS, FPUX86_HAS_AVX512F, + FPUX86_HAS_AVX512BW, + FPUX86_HAS_AVX512CD, FPUX86_HAS_AVX512VL, FPUX86_HAS_AVX512DQ );