From ff7af306df43e753d8861a353dd702633fb9a88f Mon Sep 17 00:00:00 2001
From: Jeppe Johansen <jeppe@j-software.dk>
Date: Thu, 1 Jan 2015 11:18:04 +0000
Subject: [PATCH] Add FPA support.

git-svn-id: branches/laksen/armiw@29366 -
---
 compiler/arm/aasmcpu.pas | 189 +++++++++++++++-
 compiler/arm/armatt.inc  |   2 +
 compiler/arm/armatts.inc |   2 +
 compiler/arm/armins.dat  |  74 ++++++-
 compiler/arm/armnop.inc  |   2 +-
 compiler/arm/armop.inc   |   2 +
 compiler/arm/armtab.inc  | 456 ++++++++++++++++++++++++++++++++++++++-
 rtl/arm/arm.inc          |   2 -
 8 files changed, 705 insertions(+), 24 deletions(-)

diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas
index 5a95c7e459..126a3d3222 100644
--- a/compiler/arm/aasmcpu.pas
+++ b/compiler/arm/aasmcpu.pas
@@ -1995,9 +1995,9 @@ implementation
             IF_NONE,
             IF_NONE,
             IF_NONE,
-            IF_NONE,
-            IF_NONE,
-            IF_NONE,
+            IF_FPA,
+            IF_FPA,
+            IF_FPA,
             IF_VFPv2,
             IF_VFPv2 or IF_VFPv3,
             IF_VFPv2 or IF_VFPv3,
@@ -2299,7 +2299,7 @@ implementation
         { update condition flags
           or floating point single }
       if (oppostfix=PF_S) and
-        not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30,#$60..#$6B,#$80..#$82]) then
+        not(p^.code[0] in [#$04..#$0F,#$14..#$16,#$29,#$30,#$60..#$6B,#$80..#$82,#$A0..#$A2]) then
         begin
           Matches:=0;
           exit;
@@ -2307,7 +2307,7 @@ implementation
 
       { floating point size }
       if (oppostfix in [PF_D,PF_E,PF_P,PF_EP]) and
-        not(p^.code[0] in []) then
+        not(p^.code[0] in [#$A0..#$A2]) then
         begin
           Matches:=0;
           exit;
@@ -4589,8 +4589,8 @@ implementation
                 end
               else
                 begin
-                  bytes:=bytes or (getsupreg(oper[0]^.reg) shl 0);
                   offset:=1;
+                  bytes:=bytes or (getsupreg(oper[0]^.reg) shl 0);
                 end;
 
               if oper[offset]^.typ=top_const then
@@ -5030,6 +5030,183 @@ implementation
                     message(asmw_e_invalid_effective_address);
                 end;
             end;
+          #$A0: { FPA: CPDT(LDF/STF) }
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or (ord(insentry^.code[3]) shl 8);
+              bytes:=bytes or ord(insentry^.code[4]);
+
+              if ops=2 then
+                begin
+                  bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+
+                  bytes:=bytes or getsupreg(oper[1]^.ref^.base) shl 16;
+                  bytes:=bytes or ((oper[1]^.ref^.offset shr 2) and $FF);
+                  if oper[1]^.ref^.offset>=0 then
+                    bytes:=bytes or (1 shl 23);
+
+                  if oper[1]^.ref^.addressmode<>AM_OFFSET then
+                    bytes:=bytes or (1 shl 21);
+                  if oper[1]^.ref^.addressmode=AM_PREINDEXED then
+                    bytes:=bytes or (1 shl 24);
+
+                  case oppostfix of
+                    PF_D: bytes:=bytes or (0 shl 22) or (1 shl 15);
+                    PF_E: bytes:=bytes or (1 shl 22) or (0 shl 15);
+                    PF_P: bytes:=bytes or (1 shl 22) or (1 shl 15);
+                  end;
+                end
+              else
+                begin
+                  bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+
+                  case oper[1]^.val of
+                    1: bytes:=bytes or (1 shl 15);
+                    2: bytes:=bytes or (1 shl 22);
+                    3: bytes:=bytes or (1 shl 22) or (1 shl 15);
+                    4: ;
+                  else
+                    message1(asmw_e_invalid_opcode_and_operands, 'Invalid count for LFM/SFM');
+                  end;
+
+                  bytes:=bytes or getsupreg(oper[2]^.ref^.base) shl 16;
+                  bytes:=bytes or ((oper[2]^.ref^.offset shr 2) and $FF);
+                  if oper[2]^.ref^.offset>=0 then
+                    bytes:=bytes or (2 shl 23);
+
+                  if oper[2]^.ref^.addressmode<>AM_OFFSET then
+                    bytes:=bytes or (1 shl 21);
+                  if oper[2]^.ref^.addressmode=AM_PREINDEXED then
+                    bytes:=bytes or (1 shl 24);
+                end;
+            end;
+          #$A1: { FPA: CPDO }
+            begin
+              { set instruction code }
+              bytes:=bytes or ($E shl 24);
+              bytes:=bytes or (ord(insentry^.code[1]) shl 15);
+              bytes:=bytes or ((ord(insentry^.code[2]) shr 1) shl 20);
+              bytes:=bytes or (1 shl 8);
+
+              bytes:=bytes or getsupreg(oper[0]^.reg) shl 12;
+              if ops=2 then
+                begin
+                  if oper[1]^.typ=top_reg then
+                    bytes:=bytes or getsupreg(oper[1]^.reg) shl 0
+                  else
+                    case oper[1]^.val of
+                      0: bytes:=bytes or $8;
+                      1: bytes:=bytes or $9;
+                      2: bytes:=bytes or $A;
+                      3: bytes:=bytes or $B;
+                      4: bytes:=bytes or $C;
+                      5: bytes:=bytes or $D;
+                      //0.5: bytes:=bytes or $E;
+                      10: bytes:=bytes or $F;
+                    else
+                      Message(asmw_e_invalid_opcode_and_operands);
+                    end;
+                end
+              else
+                begin
+                  bytes:=bytes or getsupreg(oper[1]^.reg) shl 16;
+                  if oper[2]^.typ=top_reg then
+                    bytes:=bytes or getsupreg(oper[2]^.reg) shl 0
+                  else
+                    case oper[2]^.val of
+                      0: bytes:=bytes or $8;
+                      1: bytes:=bytes or $9;
+                      2: bytes:=bytes or $A;
+                      3: bytes:=bytes or $B;
+                      4: bytes:=bytes or $C;
+                      5: bytes:=bytes or $D;
+                      //0.5: bytes:=bytes or $E;
+                      10: bytes:=bytes or $F;
+                    else
+                      Message(asmw_e_invalid_opcode_and_operands);
+                    end;
+                end;
+
+              case roundingmode of
+                RM_P: bytes:=bytes or (1 shl 5);
+                RM_M: bytes:=bytes or (2 shl 5);
+                RM_Z: bytes:=bytes or (3 shl 5);
+              end;
+
+              case oppostfix of
+                PF_S: bytes:=bytes or (0 shl 19) or (0 shl 7);
+                PF_D: bytes:=bytes or (0 shl 19) or (1 shl 7);
+                PF_E: bytes:=bytes or (1 shl 19) or (0 shl 7);
+              else
+                message1(asmw_e_invalid_opcode_and_operands, 'Precision cannot be undefined');
+              end;
+            end;
+          #$A2: { FPA: CPDO }
+            begin
+              { set instruction code }
+              bytes:=bytes or (ord(insentry^.code[1]) shl 24);
+              bytes:=bytes or (ord(insentry^.code[2]) shl 16);
+              bytes:=bytes or ($11 shl 4);
+
+              case opcode of
+                A_FLT:
+                  begin
+                    bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
+                    bytes:=bytes or (getsupreg(oper[1]^.reg) shl 12);
+
+                    case roundingmode of
+                      RM_P: bytes:=bytes or (1 shl 5);
+                      RM_M: bytes:=bytes or (2 shl 5);
+                      RM_Z: bytes:=bytes or (3 shl 5);
+                    end;
+
+                    case oppostfix of
+                      PF_S: bytes:=bytes or (0 shl 19) or (0 shl 7);
+                      PF_D: bytes:=bytes or (0 shl 19) or (1 shl 7);
+                      PF_E: bytes:=bytes or (1 shl 19) or (0 shl 7);
+                    else
+                      message1(asmw_e_invalid_opcode_and_operands, 'Precision cannot be undefined');
+                    end;
+                  end;
+                A_FIX:
+                  begin
+                    bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+                    bytes:=bytes or (getsupreg(oper[1]^.reg) shl 0);
+
+                    case roundingmode of
+                      RM_P: bytes:=bytes or (1 shl 5);
+                      RM_M: bytes:=bytes or (2 shl 5);
+                      RM_Z: bytes:=bytes or (3 shl 5);
+                    end;
+                  end;
+                A_WFS,A_RFS,A_WFC,A_RFC:
+                  begin
+                    bytes:=bytes or (getsupreg(oper[0]^.reg) shl 12);
+                  end;
+                A_CMF,A_CNF,A_CMFE,A_CNFE:
+                  begin
+                    bytes:=bytes or (getsupreg(oper[0]^.reg) shl 16);
+
+                    if oper[1]^.typ=top_reg then
+                      bytes:=bytes or getsupreg(oper[1]^.reg) shl 0
+                    else
+                      case oper[1]^.val of
+                        0: bytes:=bytes or $8;
+                        1: bytes:=bytes or $9;
+                        2: bytes:=bytes or $A;
+                        3: bytes:=bytes or $B;
+                        4: bytes:=bytes or $C;
+                        5: bytes:=bytes or $D;
+                        //0.5: bytes:=bytes or $E;
+                        10: bytes:=bytes or $F;
+                      else
+                        Message(asmw_e_invalid_opcode_and_operands);
+                      end;
+                  end;
+              end;
+            end;
           #$fe: // No written data
             begin
               exit;
diff --git a/compiler/arm/armatt.inc b/compiler/arm/armatt.inc
index 4f122d6716..bbf7e9301a 100644
--- a/compiler/arm/armatt.inc
+++ b/compiler/arm/armatt.inc
@@ -332,6 +332,7 @@
 'rdf',
 'rfs',
 'rfc',
+'wfc',
 'rmf',
 'rpw',
 'mnf',
@@ -341,6 +342,7 @@
 'asn',
 'atn',
 'cnf',
+'cnfe',
 'cos',
 'dvf',
 'exp',
diff --git a/compiler/arm/armatts.inc b/compiler/arm/armatts.inc
index 66da97237a..fcab30cb1c 100644
--- a/compiler/arm/armatts.inc
+++ b/compiler/arm/armatts.inc
@@ -350,5 +350,7 @@ attsufNONE,
 attsufNONE,
 attsufNONE,
 attsufNONE,
+attsufNONE,
+attsufNONE,
 attsufNONE
 );
diff --git a/compiler/arm/armins.dat b/compiler/arm/armins.dat
index 847e041520..a04ae15b88 100644
--- a/compiler/arm/armins.dat
+++ b/compiler/arm/armins.dat
@@ -127,6 +127,8 @@ reg32,reg32,immshifter      \7\x2\x80                     ARM32,ARMv4
 reg32,reg32,immshifter      \x81\xF2\x0\x0\x0             THUMB32,ARMv6T2
 
 [ADFcc]
+fpureg,fpureg,fpureg        \xA1\0\x0                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x0                     ARM32,FPA
 
 [ADRcc]
 ;reg32,immshifter           \x33\x2\x0F                   ARM32,ARMv4
@@ -238,15 +240,22 @@ reg32,reg32,shifterop    \xE\x1\x40                     ARM32,ARMv4
 reg32,immshifter         \xF\x3\x40                     ARM32,ARMv4
 
 [CMFcc]
+fpureg,fpureg            \xA2\xE\x90                    ARM32,FPA
+fpureg,immshifter        \xA2\xE\x90                    ARM32,FPA
 
 [CMFEcc]
+fpureg,fpureg            \xA2\xE\xC0                    ARM32,FPA
+fpureg,immshifter        \xA2\xE\xC0                    ARM32,FPA
 
 [STFcc]
+fpureg,memam2            \xA0\xC\x00\x1\x0              ARM32,FPA
 
 [LDFcc]
+fpureg,memam2            \xA0\xC\x10\x1\x0              ARM32,FPA
 
 [LFMcc]
-reg32,imm8,fpureg        \xF0\x02\x01                   FPA
+fpureg,imm32,memam2      \xA0\xC\x10\x2\x0              ARM32,FPA
+fpureg,immshifter,memam2 \xA0\xC\x10\x2\x0              ARM32,FPA
 
 [CLZcc]
 reg32,reg32              \x80\xFA\xB0\xF0\x80           THUMB32,ARMv6T2
@@ -387,8 +396,8 @@ reg32,reg32,reg32      \x80\xFB\x00\xF0\x00      THUMB32,ARMv6T2
 reg32,reg32,reg32      \x14\x00\x00\x90          ARM32,ARMv4
 
 [MVFcc]
-fpureg,fpureg              \xF2                      FPA
-fpureg,immfpu              \xF2                      FPA
+fpureg,fpureg               \xA1\1\x1                     ARM32,FPA
+fpureg,immshifter           \xA1\1\x1                     ARM32,FPA
 
 [MVNcc]
 reglo,reglo             \x6B\x43\xc0                    THUMB,ARMv4T
@@ -485,7 +494,8 @@ reg32,reg32,reg32,shifterop \6\x0\xC0                     ARM32,ARMv4
 reg32,reg32,immshifter      \7\x2\xC0                     ARM32,ARMv4
 
 [SFMcc]
-reg32,imm8,fpureg           \xF0\x02\x00                  FPA
+fpureg,imm32,memam2      \xA0\xC\x00\x2\x0              ARM32,FPA
+fpureg,immshifter,memam2 \xA0\xC\x00\x2\x0              ARM32,FPA
 
 [SINcc]
 
@@ -598,6 +608,7 @@ reg32,reg32,reg32,reg32     \x85\xFB\xA0\x0\x0      THUMB32,ARMv6T2
 reg32,reg32,reg32,reg32     \x16\x00\x80\x9         ARM32,ARMv4
 
 [WFScc]
+reg32                      \xA2\xE\x2               ARM32,FPA
 
 ; EDSP instructions
 [LDRDcc]
@@ -1568,57 +1579,112 @@ void                 void                          ARM32,ARMv4T
 
 
 [TANcc]
+fpureg,fpureg               \xA1\1\x15                    ARM32,FPA
+fpureg,immshifter           \xA1\1\x15                    ARM32,FPA
 
 [SQTcc]
+fpureg,fpureg               \xA1\1\x9                     ARM32,FPA
+fpureg,immshifter           \xA1\1\x9                     ARM32,FPA
 
 [SUFcc]
+fpureg,fpureg,fpureg        \xA1\0\x4                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x4                     ARM32,FPA
 
 [RSFcc]
+fpureg,fpureg,fpureg        \xA1\0\x6                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x6                     ARM32,FPA
 
 [RNDcc]
 
 [POLcc]
+fpureg,fpureg,fpureg        \xA1\0\x18                    ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x18                    ARM32,FPA
 
 [RDFcc]
+fpureg,fpureg,fpureg        \xA1\0\xA                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\xA                     ARM32,FPA
 
 [RFScc]
+reg32                      \xA2\xE\x3               ARM32,FPA
 
 [RFCcc]
+reg32                      \xA2\xE\x5               ARM32,FPA
+
+[WFCcc]
+reg32                      \xA2\xE\x4               ARM32,FPA
 
 [RMFcc]
+fpureg,fpureg,fpureg        \xA1\0\x10                    ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x10                    ARM32,FPA
 
 [RPWcc]
+fpureg,fpureg,fpureg        \xA1\0\xC                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\xC                     ARM32,FPA
 
 [MNFcc]
+fpureg,fpureg               \xA1\1\x3                     ARM32,FPA
+fpureg,immshifter           \xA1\1\x3                     ARM32,FPA
 
 [MUFcc]
+fpureg,fpureg,fpureg        \xA1\0\x2                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x2                     ARM32,FPA
 
 [ABScc]
+fpureg,fpureg               \xA1\1\x5                     ARM32,FPA
+fpureg,immshifter           \xA1\1\x5                     ARM32,FPA
 
 [ACScc]
+fpureg,fpureg               \xA1\1\x19                    ARM32,FPA
+fpureg,immshifter           \xA1\1\x19                    ARM32,FPA
 
 [ASNcc]
+fpureg,fpureg               \xA1\1\x17                    ARM32,FPA
+fpureg,immshifter           \xA1\1\x17                    ARM32,FPA
 
 [ATNcc]
+fpureg,fpureg               \xA1\1\x1B                    ARM32,FPA
+fpureg,immshifter           \xA1\1\x1B                    ARM32,FPA
 
 [CNFcc]
+fpureg,fpureg            \xA2\xE\xB0                    ARM32,FPA
+fpureg,immshifter        \xA2\xE\xB0                    ARM32,FPA
+
+[CNFEcc]
+fpureg,fpureg            \xA2\xE\xF0                    ARM32,FPA
+fpureg,immshifter        \xA2\xE\xF0                    ARM32,FPA
 
 [COScc]
+fpureg,fpureg               \xA1\1\x13                    ARM32,FPA
+fpureg,immshifter           \xA1\1\x13                    ARM32,FPA
 
 [DVFcc]
+fpureg,fpureg,fpureg        \xA1\0\x8                     ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x8                     ARM32,FPA
 
 [EXPcc]
 
 [FDVcc]
+fpureg,fpureg,fpureg        \xA1\0\x14                    ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x14                    ARM32,FPA
 
 [FLTcc]
+fpureg,reg32                \xA2\xE\x00                   ARM32,FPA
 
 [FIXcc]
+reg32,fpureg                \xA2\xE\x10                   ARM32,FPA
 
 [FMLcc]
+fpureg,fpureg,fpureg        \xA1\0\x12                    ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x12                    ARM32,FPA
 
 [FRDcc]
+fpureg,fpureg,fpureg        \xA1\0\x16                    ARM32,FPA
+fpureg,fpureg,immshifter    \xA1\0\x16                    ARM32,FPA
 
 [LGNcc]
+fpureg,fpureg               \xA1\1\xD                     ARM32,FPA
+fpureg,immshifter           \xA1\1\xD                     ARM32,FPA
 
 [LOGcc]
+fpureg,fpureg               \xA1\1\xB                     ARM32,FPA
+fpureg,immshifter           \xA1\1\xB                     ARM32,FPA
\ No newline at end of file
diff --git a/compiler/arm/armnop.inc b/compiler/arm/armnop.inc
index 10e24f7b56..53b161e2eb 100644
--- a/compiler/arm/armnop.inc
+++ b/compiler/arm/armnop.inc
@@ -1,2 +1,2 @@
 { don't edit, this file is generated from armins.dat }
-746;
+808;
diff --git a/compiler/arm/armop.inc b/compiler/arm/armop.inc
index 91e4d409ef..4c43a28c06 100644
--- a/compiler/arm/armop.inc
+++ b/compiler/arm/armop.inc
@@ -332,6 +332,7 @@ A_POL,
 A_RDF,
 A_RFS,
 A_RFC,
+A_WFC,
 A_RMF,
 A_RPW,
 A_MNF,
@@ -341,6 +342,7 @@ A_ACS,
 A_ASN,
 A_ATN,
 A_CNF,
+A_CNFE,
 A_COS,
 A_DVF,
 A_EXP,
diff --git a/compiler/arm/armtab.inc b/compiler/arm/armtab.inc
index fb9d67ebba..c36c1248c9 100644
--- a/compiler/arm/armtab.inc
+++ b/compiler/arm/armtab.inc
@@ -210,6 +210,20 @@
     code    : #129#242#0#0#0;
     flags   : if_thumb32 or if_armv6t2
   ),
+  (
+    opcode  : A_ADF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#0;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ADF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#0;
+    flags   : if_arm32 or if_fpa
+  ),
   (
     opcode  : A_ADR;
     ops     : 2;
@@ -686,12 +700,61 @@
     code    : #15#3#64;
     flags   : if_arm32 or if_armv4
   ),
+  (
+    opcode  : A_CMF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#144;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CMF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#144;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CMFE;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#192;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CMFE;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#192;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_STF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #160#12#0#1#0;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LDF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_memoryam2,ot_none,ot_none,ot_none,ot_none);
+    code    : #160#12#16#1#0;
+    flags   : if_arm32 or if_fpa
+  ),
   (
     opcode  : A_LFM;
     ops     : 3;
-    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none,ot_none,ot_none);
-    code    : #240#2#1;
-    flags   : if_fpa
+    optypes : (ot_fpureg,ot_immediate or ot_bits32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #160#12#16#2#0;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LFM;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #160#12#16#2#0;
+    flags   : if_arm32 or if_fpa
   ),
   (
     opcode  : A_CLZ;
@@ -1243,15 +1306,15 @@
     opcode  : A_MVF;
     ops     : 2;
     optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
-    code    : #242;
-    flags   : if_fpa
+    code    : #161#1#1;
+    flags   : if_arm32 or if_fpa
   ),
   (
     opcode  : A_MVF;
     ops     : 2;
-    optypes : (ot_fpureg,ot_immediatefpu,ot_none,ot_none,ot_none,ot_none);
-    code    : #242;
-    flags   : if_fpa
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#1;
+    flags   : if_arm32 or if_fpa
   ),
   (
     opcode  : A_MVN;
@@ -1718,9 +1781,16 @@
   (
     opcode  : A_SFM;
     ops     : 3;
-    optypes : (ot_reg32,ot_immediate or ot_bits8,ot_fpureg,ot_none,ot_none,ot_none);
-    code    : #240#2#0;
-    flags   : if_fpa
+    optypes : (ot_fpureg,ot_immediate or ot_bits32,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #160#12#0#2#0;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_SFM;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_memoryam2,ot_none,ot_none,ot_none);
+    code    : #160#12#0#2#0;
+    flags   : if_arm32 or if_fpa
   ),
   (
     opcode  : A_SMLAL;
@@ -2191,6 +2261,13 @@
     code    : #22#0#128#9;
     flags   : if_arm32 or if_armv4
   ),
+  (
+    opcode  : A_WFS;
+    ops     : 1;
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#2;
+    flags   : if_arm32 or if_fpa
+  ),
   (
     opcode  : A_LDRD;
     ops     : 3;
@@ -5221,5 +5298,362 @@
     optypes : (ot_none,ot_none,ot_none,ot_none,ot_none,ot_none);
     code    : #0;
     flags   : if_arm32 or if_armv4t
+  ),
+  (
+    opcode  : A_TAN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#21;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_TAN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#21;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_SQT;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#9;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_SQT;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#9;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_SUF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#4;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_SUF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#4;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RSF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#6;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RSF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#6;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_POL;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#24;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_POL;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#24;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RDF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#10;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RDF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#10;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RFS;
+    ops     : 1;
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#3;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RFC;
+    ops     : 1;
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#5;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_WFC;
+    ops     : 1;
+    optypes : (ot_reg32,ot_none,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#4;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RMF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#16;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RMF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#16;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RPW;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#12;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_RPW;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#12;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_MNF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#3;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_MNF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#3;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_MUF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#2;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_MUF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#2;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ABS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#5;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ABS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#5;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ACS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#25;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ACS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#25;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ASN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#23;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ASN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#23;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ATN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#27;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_ATN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#27;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CNF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#176;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CNF;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#176;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CNFE;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#240;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_CNFE;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#240;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_COS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#19;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_COS;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#19;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_DVF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#8;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_DVF;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#8;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FDV;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#20;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FDV;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#20;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FLT;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_reg32,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#0;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FIX;
+    ops     : 2;
+    optypes : (ot_reg32,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #162#14#16;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FML;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#18;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FML;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#18;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FRD;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none);
+    code    : #161#0#22;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_FRD;
+    ops     : 3;
+    optypes : (ot_fpureg,ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none);
+    code    : #161#0#22;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LGN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#13;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LGN;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#13;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LOG;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_fpureg,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#11;
+    flags   : if_arm32 or if_fpa
+  ),
+  (
+    opcode  : A_LOG;
+    ops     : 2;
+    optypes : (ot_fpureg,ot_immediateshifter,ot_none,ot_none,ot_none,ot_none);
+    code    : #161#1#11;
+    flags   : if_arm32 or if_fpa
   )
 );
diff --git a/rtl/arm/arm.inc b/rtl/arm/arm.inc
index 9dccb0eb12..c3243e9a3f 100644
--- a/rtl/arm/arm.inc
+++ b/rtl/arm/arm.inc
@@ -15,8 +15,6 @@
 
  **********************************************************************}
 
-{$asmmode divided}
-
 {$ifndef FPC_SYSTEM_HAS_MOVE}
 {$define FPC_SYSTEM_FPC_MOVE}
 {$endif FPC_SYSTEM_HAS_MOVE}