diff --git a/compiler/arm/aasmcpu.pas b/compiler/arm/aasmcpu.pas
index ee1f53a4a2..4df0decb06 100644
--- a/compiler/arm/aasmcpu.pas
+++ b/compiler/arm/aasmcpu.pas
@@ -161,6 +161,7 @@ uses
          constructor op_none(op : tasmop);
 
          constructor op_reg(op : tasmop;_op1 : tregister);
+         constructor op_ref(op : tasmop;const _op1 : treference);
          constructor op_const(op : tasmop;_op1 : longint);
 
          constructor op_reg_reg(op : tasmop;_op1,_op2 : tregister);
@@ -298,6 +299,15 @@ implementation
       end;
 
 
+    { for pld }
+    constructor taicpu.op_ref(op : tasmop;const _op1 : treference);
+      begin
+         inherited create(op);
+         ops:=1;
+         loadref(0,_op1);
+      end;
+
+
     constructor taicpu.op_reg(op : tasmop;_op1 : tregister);
       begin
          inherited create(op);
diff --git a/compiler/arm/narminl.pas b/compiler/arm/narminl.pas
index c6a61db6a5..d8ac36b79e 100644
--- a/compiler/arm/narminl.pas
+++ b/compiler/arm/narminl.pas
@@ -48,6 +48,7 @@ interface
         procedure second_cos_real; override;
         procedure second_sin_real; override;
         }
+        procedure second_prefetch; override;
       private
         procedure load_fpu_location;
       end;
@@ -58,6 +59,7 @@ implementation
     uses
       globtype,systems,
       cutils,verbose,globals,fmodule,
+      cpuinfo,
       symconst,symdef,
       aasmbase,aasmtai,aasmdata,aasmcpu,
       cgbase,cgutils,
@@ -211,6 +213,30 @@ implementation
       end;
     }
 
+    procedure tarminlinenode.second_prefetch;
+      var
+        ref : treference;
+        r : tregister;
+      begin
+        if current_settings.cputype>=cpu_armv5 then
+          begin
+            secondpass(left);
+            case left.location.loc of
+              LOC_CREFERENCE,
+              LOC_REFERENCE:
+                begin
+                  r:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
+                  cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,left.location.reference,r);
+                  reference_reset_base(ref,r,0);
+                  { since the address might be nil we can't use ldr for older cpus }
+                  current_asmdata.CurrAsmList.concat(taicpu.op_ref(A_PLD,ref));
+                end;
+              else
+                internalerror(200402021);
+            end;
+          end;
+      end;
+
 begin
   cinlinenode:=tarminlinenode;
 end.