411 Commits

Author	SHA1	Message	Date
florian	47d2395110	* set operand size properly for STX*	2024-07-08 21:54:05 +02:00
florian	b974e4a25f	* fix extension to 64 bit on aarch64, resolves #40576	2024-07-07 16:36:29 +02:00
florian	8cafafc3e6	+ add missing instructions	2024-07-05 21:06:21 +02:00
florian	6c50c02f7c	* bail out early in tcgaarch64.make_simple_ref if possible	2024-06-17 22:54:06 +02:00
J. Gareth "Curious Kit" Moreton	bf970b29f4	* arm / a64: TAsmNode debugging info is now output for ARM and AArch64	2024-05-30 20:04:11 +00:00
J. Gareth "Curious Kit" Moreton	605b21af8c	* a64: win64 implementation of jump table now ... uses 64-bit absolute references.	2024-05-27 06:31:15 +01:00
florian	f49da05633	* unified g_concatcopy_move	2024-05-15 22:52:24 +02:00
J. Gareth "Curious Kit" Moreton	88ab9576b1	* a64: Added "ABS" and "CTZ" mnemonics (CSSC instructions)	2024-04-21 09:06:16 +00:00
J. Gareth "Curious Kit" Moreton	1ba93085f7	* a64: Added DOTPROD and PAUTH support flags to relevant instruction sets (v8.4+ and v8.3+ respectively)	2024-04-21 09:06:16 +00:00
J. Gareth "Curious Kit" Moreton	bba4edb6d0	* a64: ARMv8.7 through ARMv8.9 have been added as AArch64 CPU types, along with support for the CSSC extension.	2024-04-21 09:06:16 +00:00
florian	9409ec6341	* workaround unsupported -march=...+pauth for some assembler/clang versions	2024-04-21 11:04:42 +02:00
J. Gareth "Curious Kit" Moreton	9ee1821622	* arm / a64: Extended the AND; CMP -> ANDS family of optimisations to catch BIC as well as AND	2024-04-20 12:55:47 +00:00
J. Gareth "Curious Kit" Moreton	77c86cafd0	* a64: Fixed bug where unsigned min/max inlines used a signed comparison	2024-03-26 14:18:31 +00:00
J. Gareth "Curious Kit" Moreton	81b7b80749	* Added support for 64-bit min/max intrinsics	2024-03-26 14:18:31 +00:00
J. Gareth "Curious Kit" Moreton	2b7df4237b	* nf_pass1_done, nf_error, nf_processing and nf_do_not_execute ... have been moved to a new "transientflags" node field that isn't stored in PPU files	2024-03-24 18:14:49 +00:00
J. Gareth "Curious Kit" Moreton	99851f22f5	* a64: New B -> RET peephole optimisation	2024-03-24 13:31:52 +00:00
florian	20f9b82543	* AArch64: overflow checking for abs ... * tabs adapted: also abs(longint) must overflow check on 64 bit platforms	2024-03-24 12:47:16 +01:00
florian	1fccfd3ee1	* AArch64: avoid false overflow error in case of -2^63+0	2024-03-24 12:36:02 +01:00
J. Gareth "Curious Kit" Moreton	a907eb49c9	* a64: Several secondary peephole optimizations that clean up CSEL instructions	2024-03-15 18:08:37 +00:00
J. Gareth "Curious Kit" Moreton	ef1cb852a8	* a64: New CSEL block optimisations ported over from x86 CMOV block optimisations	2024-03-15 18:08:37 +00:00
Michaël Van Canneyt	4e8b1cb97a	* Fixed signature of insert_init_final_table	2024-03-05 07:56:14 +00:00
florian	a71cc71585	+ function needs_check_for_fpu_exceptions to unify fpu exception handling	2024-02-13 17:42:21 +01:00
florian	3ed5a4a022	+ when calling FPC_THROWFPUEXCEPTION in a sub routine, pi_do_call must be set, fixed for aarch64	2024-02-12 23:25:35 +01:00
J. Gareth "Curious Kit" Moreton	bf29f2051c	* arm/a64: Added new TST post-peephole optimisation to replace previous AND/CMP/B(c) optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	b18c10d0d8	* arm/a64: New "OptPass2TST" routine to catch "TST; B.c; AND -> ANDS; B.c" optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	9f19f582c4	* arm/a64: New AND/CMP -> TST or ANDS optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	38d2f3d58c	* a64: Renamed OptPostCMP/And to PostPeepholeOptCMP/AND for internal consistency	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	72081c803e	* a64: SkipAligns calls removed.	2023-12-29 14:17:08 +00:00
J. Gareth "Curious Kit" Moreton	afe2e80673	* a64: Node parser now attempts to directly create BIC, ORN and EON instructions	2023-11-08 21:07:00 +00:00
J. Gareth "Curious Kit" Moreton	23e514621d	* a64: Corrected supported shifter/extender mnemonics for arithmetic/logical instructions	2023-10-22 13:13:58 +00:00
J. Gareth "Curious Kit" Moreton	bb2e626fc3	* a64: Fixed bug where BIC instructions were treated as having 2 operands rather than 3	2023-10-22 13:13:58 +00:00
J. Gareth "Curious Kit" Moreton	82a8640111	* a64: New conditional branch to CSET peephole optimisation	2023-10-22 12:16:50 +00:00
florian	657f3c52bf	* according to Jonas iOS doesn't zero extend results in the callee either, so check removed	2023-09-12 23:05:48 +02:00
florian	a517ada539	* on aarch64-darwin, the unused part of function results is not cleared	2023-09-10 19:27:21 +02:00
Pierre Muller	5a123d33ba	Add -Awin64-as option for aarch64 compiler for win64 target	2023-05-26 11:15:55 +00:00
Dmytro Bogatskyy	327aac7f24	Add aarch64-iphonesim target	2023-03-27 18:45:00 +00:00
florian	dfb8794d4d	* compilation after merge fixed	2023-01-25 20:44:34 +01:00
Pierre Muller	aaa6f0d9c5	Only signed extension is needed	2023-01-25 19:36:45 +00:00
Pierre Muller	4793447be1	Add sign extension to 32-bit for unaligned OS_8 and OS_16 types (to try to solve #40102)	2023-01-25 19:36:45 +00:00
Pierre Muller	cd8aa3f0e0	Avoid generation of invalid 'cb(n)z sp,label' instruction	2023-01-02 18:22:49 +00:00
florian	4430422489	* improve module local data accesses by avoiding a got read	2022-12-28 22:05:23 +01:00
Jonas Maebe	851af5033f	Darwin/AArch64: adjust alignment info of custom-aligned paralocs ... Resolves #40019	2022-12-06 21:46:26 +01:00
Jonas Maebe	230142e183	AArch64 cgcpu: add missing brackets around and/or expression	2022-12-03 21:17:18 +01:00
Jonas Maebe	cd8ddffe42	AArch64: X18 is not a volatile register ... It may be unused on some platforms, but in general it's reserved for OS library usage (usually related to TLS)	2022-10-29 14:24:37 +02:00
florian	3a11ee9a14	* apply OptPass1Data to neg as well	2022-09-06 21:42:29 +02:00
florian	5cbb36f218	* factor out TARMAsmOptimizer.USxtOp2Op	2022-09-03 19:21:28 +02:00
florian	ed7b0c5e68	* AArch64: extended SxtwMov2Data to CMP and CMN	2022-09-03 19:03:48 +02:00
florian	ad1c19864d	* small refactoring	2022-09-01 21:44:18 +02:00
florian	9adcc891cf	+ Aarch64: SxtwOp2Op optimization	2022-09-01 21:44:18 +02:00
florian	29495c9ba5	* refactor TCpuAsmOptimizer.OptPass1SXTW	2022-09-01 21:44:18 +02:00