13 Commits

Author	SHA1	Message	Date
florian	425ef662cc	* patch by Pierre to fix spilling and jump handling of pseudo-instructions	2025-03-31 22:53:40 +02:00
florian	5bb4049737	* remove accidently committed debug statement	2025-01-12 11:32:34 +01:00
florian	971d97c179	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
florian	1202b2612f	+ RiscV: make use of the fl* rd,symbol,rd pseudoinstruction	2025-01-11 14:22:01 +01:00
florian	c3110dfaa9	+ RiscV: make use of the fneg.* instruction	2025-01-09 22:25:26 +01:00
florian	2c5a070959	+ random bits for quad support on RiscV	2025-01-06 15:21:18 +01:00
florian	27a0da5a20	* typo corrected	2024-12-02 22:45:34 +01:00
florian	6ef37d999a	+ Risc-V: instructions of B extension	2024-08-12 21:51:22 +02:00
florian	a05aa25aad	* Risc-V: allow also register aliases in register modification lists after asm blocks, last part to resolve #39738	2022-06-03 22:54:18 +02:00
florian	ec3a04da9b	+ forgotten pseudo-instructions added	2022-06-01 22:31:26 +02:00
florian	eaeb8b70ff	+ added Risc-V register information file generation to the compiler Makefile ... * more stringent naming of register file information for Risc-V	2022-05-31 22:38:30 +02:00
florian	4556cb35d1	+ completed Risc-V 64 pseudo instructions ... * typo fixed	2022-05-28 21:22:11 +02:00
florian	6a00f9f403	* unified Risc-V 32 and 64 cpubase.pas	2022-05-28 21:15:53 +02:00