Commit Graph

13 Commits

Author SHA1 Message Date
florian
15b3f16646 * use fld1/fchs regardless of pic 2024-06-06 22:36:29 +02:00
florian
aaeefacf85 * also optimize loading of -1.0 2024-06-05 22:56:45 +02:00
florian
8c2aca6ece * load 2 on x86 stack by fld1/fadd, if pic code is generated. It is more efficient as two memory accesses are saved. 2024-06-04 23:21:26 +02:00
florian
01d6358f93 * some fixes for expectloc 2021-09-22 22:09:19 +02:00
florian
9bd785c06b * fix handling of -0.0 in sse/avx code, resolves #39357 2021-09-13 22:47:26 +02:00
florian
8e62bf649e * load 0.0 by (V)XORPS/D instead of (V)PXOR in mm registers
git-svn-id: trunk@47073 -
2020-10-10 13:23:35 +00:00
florian
36d21d2d81 + use pxor/vpxor to load 0.0
git-svn-id: trunk@47053 -
2020-10-05 20:11:41 +00:00
florian
45f60bc4b5 * small changes (copyright, typo, readability)
git-svn-id: trunk@23022 -
2012-11-18 17:28:30 +00:00
Jonas Maebe
d1538ab023 o added ARM VPFv2/VFPv3 support:
+ RTL support:
      o VFP exceptions are disabled by default on Darwin,
        because they cause kernel panics on iPhoneOS 2.2.1 at least
      o all denormals are truncated to 0 on Darwin, because disabling
        that also causes kernel panics on iPhoneOS 2.2.1 (probably
        because otherwise denormals can also cause exceptions)
    * set softfloat rounding mode correctly for non-wince/darwin/vfp
      targets
    + compiler support: only half the number of single precision
      registers is available due to limitations of the register
      allocator
    + added a number of comments about why the stackframe on ARM is
      set up the way it is by the compiler
    + added regtype and subregtype info to regsets, because they're
      also used for VFP registers (+ support in assembler reader)
    + various generic support routines for dealing with floating point
      values located in integer registers that have to be transferred to
      mm registers (needed for VFP)
    * renamed use_sse() to use_vectorfpu() and also use it for
      ARM/vfp support
    o only superficially tested for Linux (compiler compiled with -Cpvfpv6
      -Cfvfpv2 works on a Cortex-A8, no testsuite run performed -- at least
      the fpu exception handler still needs to be implemented), Darwin has
      been tested more thoroughly
  + added ARMv6 cpu type and made it default for Darwin/ARM
  + ARMv6+ implementations of atomic operations using ldrex/strex
  * don't use r9 on Darwin/ARM, as it's reserved under certain
    circumstances (don't know yet which ones)
  * changed C-test object files for ARM/Darwin to ARMv6 versions
  * check in assembler reader that regsets are not empty, because
    instructions with a regset operand have undefined behaviour in that
    case
  * fixed resultdef of tarmtypeconvnode.first_int_to_real in case of
    int64->single type conversion
  * fixed constant pool locations in case 64 bit constants are generated,
    and/or when vfp instructions with limited reach are present

  WARNING: when using VFP on an ARMv6 or later cpu, you *must* compile all
    code with -Cparmv6 (or higher), or you will get crashes. The reason is
    that storing/restoring multiple VFP registers must happen using
    different instructions on pre/post-ARMv6.

git-svn-id: trunk@14317 -
2009-12-03 22:46:30 +00:00
peter
6b8aed593f * remove registers{int/mmx/fpu} from firstpass
* small cleanups of unused variables in firstpass
  * node_resources_fpu() created to get an approximation of the
    required fpu registers
  * for the moment use node_complexity in the CG until the
    node_resource_int() is created

git-svn-id: trunk@8655 -
2007-09-26 21:12:01 +00:00
peter
3078a1927f * remove ttype
* rename old ttype variables *type to *def
  * rename resulttypepass to pass_typecheck
  * rename pass_2 to pass_generate_code

git-svn-id: trunk@5077 -
2006-10-29 22:19:39 +00:00
Jonas Maebe
6ad5dff9e8 * fixed loading of -0.0
git-svn-id: trunk@2976 -
2006-03-19 20:29:15 +00:00
florian
ebcb69478f * fixed a lot of stuff for fpu/mm register variables
git-svn-id: trunk@199 -
2005-06-04 21:23:15 +00:00