Nikolay Nikolov
c9ed14f87b
+ enable the 64-bit SAR instruction on the WebAssembly target
2022-05-27 22:56:05 +03:00
Nikolay Nikolov
b6aaa06f83
+ enable the ROL/ROR instructions for WebAssembly
2022-05-27 22:46:32 +03:00
Jeppe Johansen
74a7963d58
Redo overflow checking code.
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Fix shift operators in case of unsigned subreg operations. There should be no sign extension here.
Add some unittest implementations that test stack execution and writing to readonly constants.
git-svn-id: branches/laksen/riscv_new@39762 -
2018-09-16 18:37:59 +00:00
pierre
e518bd52ba
Explicitly disabled overflow and range check for these two tests
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git-svn-id: trunk@39266 -
2018-06-21 04:52:37 +00:00
nickysn
504662826a
* fixed the rtl cpu ifdefs for the rol/ror/sar cpu support check
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git-svn-id: trunk@36153 -
2017-05-08 10:16:15 +00:00
nickysn
4a8a7c210a
* fixed test on platforms that don't have 8-bit and 16-bit rol/ror
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git-svn-id: trunk@36144 -
2017-05-07 13:34:26 +00:00
nickysn
881cb790a9
+ added tests that check side effect removal behaviour for the simplifications
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added/changed today
git-svn-id: trunk@36053 -
2017-05-01 21:01:26 +00:00
