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03dfa07ebc
Commit Graph

20089 Commits

Author SHA1 Message Date
nickysn
03dfa07ebc + implemented OP_SHR/OP_SHL/OP_SAR in i386's tcg64f386.a_op64_reg_ref 
git-svn-id: trunk@35834 -
 2017-04-18 14:34:20 +00:00
pierre
17b2671213 Regenerate all Makefile's after changes related to FPCDIR checks 
git-svn-id: trunk@35833 -
 2017-04-18 14:15:47 +00:00
nickysn
3d28878210 + added taicpu.op_reg_reg_ref() constructor for x86, in order to support the 
shld/shrd [ref],reg,CL instructions

git-svn-id: trunk@35832 -
 2017-04-18 12:47:57 +00:00
nickysn
10d7603dce + implemented OP_SHR/OP_SHL/OP_SAR support in tcg64f386.a_op64_reg_reg 
git-svn-id: trunk@35831 -
 2017-04-18 12:24:46 +00:00
nickysn
7e8c89435f * avoid the AND instruction in the i386 shr64/shl64 code, by using TEST+JZ, 
instead of CMP+JL

git-svn-id: trunk@35830 -
 2017-04-18 11:36:48 +00:00
Jonas Maebe
4e1f999b02 * write full path name when ppu crc checks fail/conflict (patch by 
C. Western, mantis #31650)

git-svn-id: trunk@35823 -
 2017-04-17 20:42:03 +00:00
nickysn
b14f277e8f + use rtl helpers for 64-bit shl/shr/sar/rol/ror modify in place operations, on 
platforms that don't have native 64-bit implementation of the corresponding
  64-bit shift/rotate operation

git-svn-id: trunk@35787 -
 2017-04-13 15:24:32 +00:00
nickysn
a1ad705646 + allocate and free flags before and after the shl+rcl/shr+rcr/sar+rcr sequences 
git-svn-id: trunk@35786 -
 2017-04-13 11:58:51 +00:00
nickysn
cddb48bad4 + i386 implementation of a_op64_const_reg for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35785 -
 2017-04-13 11:54:19 +00:00
nickysn
6a710964f2 + i386 implementation of a_op64_const_ref for OP_SHR,OP_SHL and OP_SAR; needed 
by the in_shl/shr/sar_assign_x_y inline nodes

git-svn-id: trunk@35784 -
 2017-04-13 10:38:33 +00:00
nickysn
599b9e73de * determine correctly whether operand size is 32 or 64 bits for 
sar/shl/shr/rol/ror in tcginlinenode.second_AndOrXorShiftRot_assign

git-svn-id: trunk@35783 -
 2017-04-12 13:36:42 +00:00
nickysn
b6d05dba9e * mark the sar/shl/shr/rol/ror_assign nodes as having side effects 
git-svn-id: trunk@35781 -
 2017-04-12 12:17:08 +00:00
nickysn
f514657e45 + implemented the sar/shl/shr/rol/ror inline modify-in-place nodes; the actual 
optimization of "i:=i shl/shr k", etc statements is not performed yet

git-svn-id: trunk@35780 -
 2017-04-12 00:41:15 +00:00
nickysn
7b40bdaa6e + treat the new modify-in-place inline nodes as having side effects in 
check_for_sideeffect()

git-svn-id: trunk@35774 -
 2017-04-11 14:59:38 +00:00
nickysn
5bb77905cd * fixed the missing warnings for unused variables at -O3, when one of the new 
modify-in-place inline nodes are used

git-svn-id: trunk@35773 -
 2017-04-11 14:25:57 +00:00
nickysn
4697a653a4 + perform the "i:=i +/-/and/or/xor k" optimization when there are two typecasts 
inserted. This makes the optimization work for more integer types.

git-svn-id: trunk@35772 -
 2017-04-11 11:25:40 +00:00
nickysn
8d885ffde6 + write the inlinenumber of inline nodes in the node tree 
git-svn-id: trunk@35764 -
 2017-04-10 14:54:50 +00:00
nickysn
d8406c4227 + perform the "i:=-i" / "i:=not i" optimization even when there are typecasts 
inserted; this makes the optimization work for all integer types

git-svn-id: trunk@35763 -
 2017-04-10 14:06:19 +00:00
nickysn
98be270adb * fixed a memory leak in the "i:=-i" / "i:=not i" optimization 
git-svn-id: trunk@35762 -
 2017-04-10 13:27:29 +00:00
nickysn
876c0c5fd5 + added helper function are_equal_ints() 
git-svn-id: trunk@35761 -
 2017-04-10 13:22:50 +00:00
nickysn
e78f0aafcd - remove whitespace, was inserted by accident 
git-svn-id: trunk@35760 -
 2017-04-10 11:55:26 +00:00
nickysn
3616627d0b * at -O3 optimization level, convert "i:=not i" and "i:=-i" to the new 
in_not_assign_x and in_neg_assign_x inline nodes, which may generate better
  code on certain cpus (such as x86)

git-svn-id: trunk@35758 -
 2017-04-09 14:55:15 +00:00
nickysn
9187825e3a * fixed tnegnotassign1.pp on powerpc and other RISC cpus 
git-svn-id: trunk@35757 -
 2017-04-09 14:28:13 +00:00
nickysn
c6680a32d7 * also support LOC_CREGISTER and LOC_CREFERENCE in in_not_assign_x and in_neg_assign_x 
git-svn-id: trunk@35751 -
 2017-04-07 21:33:56 +00:00
nickysn
6b43705437 * fixed compiler internal error when the in_not_assign_x/in_neg_assign_x are 
applied to a LOC_REGISTER variable

git-svn-id: trunk@35750 -
 2017-04-07 19:16:00 +00:00
nickysn
256dc546ac + implemented the in_neg_assign_x and in_not_assign_x inline nodes, which will 
be used (TBD in a future commit) for optimizing x:=-x and x:=not x on CPUs
  that support performing these operations directly in memory (such as x86)

git-svn-id: trunk@35749 -
 2017-04-07 16:02:40 +00:00
svenbarth
8024fcd7ec * if an operator overload in a structured type is invalid print an error only for the declaration and not the implementation as well 
This fixes Mantis #31634 as far as I see it useful to; anything further would probably require extension of the message generation system by a context or such so that the compiler could write "Error in TFoo<Integer>: ..." instead of merely "Error: ..." or something like that.
No test added due to the nature of the bug.

git-svn-id: trunk@35748 -
 2017-04-07 13:24:58 +00:00
nickysn
199574c7c6 * updated the compiler source files list in ppc8086.lpi 
git-svn-id: trunk@35747 -
 2017-04-07 12:40:20 +00:00
yury
ea61dee00b * ppudump: Mark objects with abstract methods in the JSON/XML output. 
* pas2jni: Properly handle inherited classes when an ancestor has abstract methods.

git-svn-id: trunk@35746 -
 2017-04-07 09:53:54 +00:00
nickysn
9093047a7a * fixed a bug in the i8086 32-bit rol/ror code generation method rm_fast_386 
git-svn-id: trunk@35745 -
 2017-04-06 15:55:43 +00:00
nickysn
1560f20e7f + implemented other 32-bit rol/ror by const methods for i8086 and added a 
(hopefully) reasonable selection for them for all consts between 1 and 31

git-svn-id: trunk@35744 -
 2017-04-06 15:41:39 +00:00
nickysn
0fd860d9e7 * refactored the code generation for 32-bit rol/ror by const for i8086, so it 
uses less code repetition and allow choosing various methods (some of which
  will be implemented later and selected, according to the cpu and optimization
  settings (size vs speed))

git-svn-id: trunk@35743 -
 2017-04-06 13:59:53 +00:00
nickysn
d5e33cce7f * generate better i8086 code for ror32 by 1 and 17 
git-svn-id: trunk@35741 -
 2017-04-05 14:16:00 +00:00
maciej-izak
ff28d5c85d * Fix usage of class operators in generics types. If we have generic type declaration/implementation then constraint in comparison to not specialized generic is not "exact" nor "incompatible". Mantis #30534. 
git-svn-id: trunk@35740 -
 2017-04-05 13:47:21 +00:00
maciej-izak
e4565378db * Allow for "record constraint" in Delphi mode more types like: ordinal, float, classical objects, enumerations (instead of just record). Delphi compatibility. Fix for mantis #24073. 
git-svn-id: trunk@35739 -
 2017-04-05 13:12:30 +00:00
nickysn
321876252b + enabled the rol/ror intrinsic on i8086 
git-svn-id: trunk@35734 -
 2017-04-04 22:37:58 +00:00
nickysn
0b1a54f924 * on 16-bit CPUs, avoid the unnecessary 32-bit conversion of the right shl/shr 
parameter, when the operation is 32-bit (even when the operation is 32-bit,
  the shift count is only 16-bit on 16-bit CPUs, so using 32-bits is wasting an
  extra register and an extra instruction to initialize it)

git-svn-id: trunk@35733 -
 2017-04-04 21:01:20 +00:00
nickysn
b957b65ec8 * generate better i8086 code for 64-bit shl/shr, by masking the shift count by 63 
git-svn-id: trunk@35730 -
 2017-04-04 17:58:00 +00:00
nickysn
6580dfee39 * generate better i386 code for 64-bit shl/shr, by masking the shift count by 
63, instead of comparing it to 64 and branching. Note that, although this
  changes the behaviour of 64-bit shifts by values larger than 64 (when stored
  in a variable), it actually makes them consistent with both the code,
  generated on x86_64, as well as with 64-bit shift by constant on i386 itself.

git-svn-id: trunk@35727 -
 2017-04-04 16:28:54 +00:00
nickysn
76cb419241 * use 16-bit 386+ instructions (shld,shrd) for performing fast 32-bit 
shl/shr/sar on i8086, in a_op_const_reg, when the target CPU is set to 80386
  or later

git-svn-id: trunk@35726 -
 2017-04-04 14:40:29 +00:00
nickysn
0ab4f01668 * implemented fast (loopless) 32-bit shift by constant for 8086 as well 
git-svn-id: trunk@35725 -
 2017-04-03 21:04:59 +00:00
maciej-izak
8391b73206 * Virtual methods cannot be declared as static (static virtual method has no sense). 
+ added tests

git-svn-id: trunk@35724 -
 2017-04-03 20:45:52 +00:00
nickysn
0f2ad7b712 * generate faster (i.e. loopless) code for 32-bit shl/shr/sar by const on 186+ 
git-svn-id: trunk@35723 -
 2017-04-03 20:37:21 +00:00
maciej-izak
ee4ae1254f undo accidental commit (r35721) :/ 
git-svn-id: trunk@35722 -
 2017-04-03 17:10:20 +00:00
maciej-izak
b4b87a841c git-svn-id: trunk@35721 - 2017-04-03 17:08:01 +00:00
florian
4504648ec1 * initialize maskvalue to fix compilation with -O3+ 
git-svn-id: trunk@35707 -
 2017-04-01 19:03:35 +00:00
nickysn
2fc62d0177 * reserve consecutive inline numbers for the other modify-in-place inline nodes 
that I'm planning to implement (sar/shl/shr/rol/ror/not/neg)

git-svn-id: trunk@35686 -
 2017-03-29 16:13:40 +00:00
nickysn
f29492bdea * at -O3 level, convert i:=i and/or/xor k to the new in_[and/or/xor]_assign_x_y 
inline nodes, which should generate better code for certain CPU targets,
  including x86. Note that the optimization isn't applied yet for all integer
  types (those that have extra implicit typecasts, inserted by the compiler,
  aren't handled yet).

git-svn-id: trunk@35685 -
 2017-03-29 15:20:57 +00:00
nickysn
f19ebe2acf * fixed compiler internal error in the in_[and/or/xor]_assign_x_y inline nodes 
when their second parameter is a large 64-bit unsigned constant

git-svn-id: trunk@35684 -
 2017-03-29 14:55:07 +00:00
nickysn
8033392554 * on 16-bit CPUs remove unnecessary 32-bit conversions of integers, that are 
later converted back to 16 bits

git-svn-id: trunk@35679 -
 2017-03-29 10:49:32 +00:00