Jeppe Johansen
2678522db5
- RISC-V: Add controller types for common RV32 MCUs.
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- Adds initial controller units for these MCUs.
Code contributed by Michael Ring
git-svn-id: trunk@43935 -
2020-01-13 22:54:26 +00:00
svenbarth
114c27fb4e
* increase support for multilib binutils for RISC V by passing the ABI to the assembler
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git-svn-id: trunk@43788 -
2019-12-25 15:23:21 +00:00
Jeppe Johansen
a1a17447ff
- Fix bug in 64bit softfloat double negation.
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- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.
git-svn-id: trunk@42335 -
2019-07-07 11:32:27 +00:00
Jonas Maebe
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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be introduced by the next commit
git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jeppe Johansen
29ea4ed07d
Add rounding mode operands.
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Add support for trunc and round methods.
git-svn-id: branches/laksen/riscv_new@39698 -
2018-09-01 19:48:44 +00:00
Jeppe Johansen
f781c8942e
Write real atomic operations, and add memory barrier operations.
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Add support for fence, and acquire/release syntax to assembler reader.
Fix broken register aliases.
git-svn-id: branches/laksen/riscv_new@39524 -
2018-07-29 16:43:09 +00:00
Jeppe Johansen
6352328f3a
Update packages with information about RiscV.
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Fix g_external_wrapper, since it uses a register.
Fixed calling of gas.
Ported cprt0.
git-svn-id: branches/laksen/riscv_new@39475 -
2018-07-20 10:40:28 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
