* It is now only used to select size of vector instructions (i.e. 128 or 256 bits)
* Scalar instructions reverted to use attsufINT suffix (selecting between 32 or 64 bits).
* Additionally, vcvtsi2sd and vcvtsi2ss with rm64 operand are x86_64 only.
git-svn-id: trunk@34942 -
* tb0267.pp required patching due to 'fildw' instruction at line 72, which is rejected by GAS. Before this commit, FPC was silently converting it to 'filds', so it went unnoticed. Now FPC rejects 'fildw' like GAS does.
git-svn-id: trunk@17363 -
+ Added new value TAttSuffix.attsufINTdual, assigned it to movsX and movzX instructions
* Moved suffix-to-size translation tables from rax86att.pas to itcpugas.pas
+ Added x86_64 specific suffix-to-size translation, enabling BQ and WQ suffixes (LQ seems unnecessary at the moment)
* Fixed logic of tx86attreader.is_asmopcode so it only assigns dual suffix to instructions that explicitly allow it. This disambiguates cases like movsbq=movs+bq vs. cmovbq=cmovb+q
* As a net result: movz[bw]q and movs[bw]q now compile for x86_64; cmovbw and cmovbl which were incorrectly handled for i386 are now fixed.
+ Test for correct assembling of cmov.
git-svn-id: trunk@17353 -
- {$intpromotion common_type} or -CIcommon_type switches to common type promotion.
- {$intpromotion native_integer} or -CIcommon_type switches to current behaviour.
- Default in tp mode is common_type, native_integer in other modes
- Compiler can cycle with -CIcommon_type
- Still needs checking on other architectures than i386
git-svn-id: trunk@8118 -
