the i8086 internal object writer. This allows weeding out spurious 386
instructions, as is similarly done by NASM when using it as an external
assembler.
git-svn-id: trunk@32871 -
the i8086 bugs, related to code that assumes that they are the same)
+ also added RELOC_RELATIVE32 on i8086
* RELOC_ABSOLUTE32 and RELOC_RELATIVE32 are not yet implemented in the OMF
object writer and linker (and currently produce an internal error), but will
be implemented in the future, as the OMF format supports both 16-bit and
32-bit relocations
git-svn-id: trunk@32311 -
It fixes PIC code generation with GOT for i386 with enabled optimizations. Bugs #28667, #28668.
Prior the fix I have not been able to compile even RTL with -O2 due to not enough free registers, since EBX is reserved for GOT.
It can be further optimized to teach register allocator to not spill the GOT register if possible.
git-svn-id: trunk@32020 -
the condition inverted; this will be used to simulate near conditional jumps
on processors earlier than 386 (i.e. "Jcc near target" will be encoded as
"JNcc short +3; JMP target")
git-svn-id: trunk@30611 -
language, An optimization guide for x86 platforms, Page 87), so restored the 32 Bit part of the old alignment
bytes for use on those old CPUs and use it depending on the CPU switches
git-svn-id: trunk@29777 -
segment to survive e.g. several nested vecnodes, which cause the base register
to change from BP to something else. In the cases where the ss: prefix is not
needed, it is removed by make_simple_ref.
+ remove the ss: prefix in the several cases where make_simple_ref isn't called
(namely spilling and tcg8086.a_call_reg_far)
git-svn-id: trunk@27714 -
o Return the correct operation type for all forms of IMUL in
taicpu.spilling_get_operation_type
o Properly support 3-op IMUL in trgx86.do_spill_replace
git-svn-id: trunk@26514 -
temp we allocate, we set the base register to a newly allocated
R_TEMPREGISTER. This allows for uniquely identifying a temp even if its
offset is modified.
git-svn-id: branches/hlcgllvm@26033 -
differentiate between 64 bit and 128 bit (R_SUBMMWHOLE) SSE vector regs,
and support spilling/assembling for R_SUBQ SSE registers (8 bytes)
(mantis #23962)
We currently never use the full 128 bit of an SSE register, and
spilling for those hasn't been implemented yet either (R_SUBMMWHOLE
SSE regs are spilled into a 4-byte temp currently -> can overwrite data)
git-svn-id: trunk@23700 -
* Adjust rip-relative offsets using values known from calcsize, instead of reinterpreting the tail of instruction. This is simpler and remains the same regardless of particular codes used in opcode table.
* Reduced maxinfolen to 8.
- 'jmp imm64' and 64-bit versions of 'in' do not exist, removed.
git-svn-id: trunk@17546 -
* Optimized the opcode representation of movq and remaining 3DNow instructions
* Disallow immediates not fitting in 32 bits (Mantis #14685) + test
* Disallow push/pop with 32-bit operands in x86_64 + test
git-svn-id: trunk@17490 -
* Factored repeating REX operations into a separate function.
* Fixed instruction matching bug which was preventing compilation of 3-operand SIMD instructions with RIP-relative operand + test.
* Do not adjust offset of RIP-relative reference if it is a literal number, this was causing 0x123(%rip) to assemble as 0x122(%rip) in 3-operand instructions. Now tasm2.pp is the same with and without -Aas. Also fixed the expected result, improved verbosity of diagnostic and removed %norun, so it is actually executed.
+ Disallow high-byte registers in instructions requiring REX + test.
git-svn-id: trunk@17478 -
* Simplified REX handling: instead of useless adjusting instruction length on every REX change, adjust it just once, based on the final REX value.
* Similar for omitting REX.W in certain instructions: set a flag and consider it once the entire instruction has been processed. This removes the requirement for \335 to be the last opcode.
* maybewriterex also after $F2 prefix
* Fixed behavior of codes \310 and \311 (16- and 32-bit address respectively), this is needed for a few fancy instructions like LOOP and JCXZ, which honor address-size prefix instead of REX.
+ control code \361 for $66 prefix
+ IF_SSSE3, IF_SSE41, IF_SSE42 instruction flags (with dummy values)
x86/x86ins.dat:
* replaced literal $67 prefixes with \310 or \311
* marked encodings containing code \310 as NOX86_64
* replaced literal $48 prefixes with \326
git-svn-id: trunk@17433 -
* Modified taicpu.Pass2 to exclude non-definitely assigned variable and issue InternalError if impossible segment prefix is used.
git-svn-id: trunk@17374 -
relocations for addr_pic_no_got references (do not go via the GOT)
* fixed code generator so that it generates addr_pic_no_got references
also for platforms that use the internal assembler (this will break linking
of some tests that check static data > 2GB on Linux/x86-64, but they were
already broken before as well because we don't use the "huge" x86-64
execution model)
* fixed x86-64 Linux syscall code to not expect GOT-based relocations for
the system unit's errno variable (it's an implementation-only variable)
git-svn-id: trunk@16717 -
a) it's unnecessary
b) it's slower than "direct" RIP-relative accessing
c) it's not supported on darwin/x86_64 in certain cases
* never use absolute addressing on darwin/x86_64 (like on win64)
* when not generating PIC, make sure that a_loadaddr_ref_reg on x86_64
also uses RIP-relative addressing for darwin/x86_64 and win64
git-svn-id: trunk@13760 -
* Suppressed 2 unreachable code warnings.
* Now x86 compiler compiles without warnings and notes! It will be great to keep such state in future...
git-svn-id: trunk@11455 -
- {$intpromotion common_type} or -CIcommon_type switches to common type promotion.
- {$intpromotion native_integer} or -CIcommon_type switches to current behaviour.
- Default in tp mode is common_type, native_integer in other modes
- Compiler can cycle with -CIcommon_type
- Still needs checking on other architectures than i386
git-svn-id: trunk@8118 -
