Jeppe Johansen
02c3f328a2
- RISC-V: Share optimizations between 32 and 64-bit.
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git-svn-id: trunk@43934 -
2020-01-13 22:49:23 +00:00
Jonas Maebe
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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be introduced by the next commit
git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jeppe Johansen
d33b520690
Clean up peephole optimization code.
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Add hardfloat ABI option for RiscV. Still needs proper implementation though.
Add CG support for profiling.
git-svn-id: branches/laksen/riscv_new@39798 -
2018-09-24 17:15:22 +00:00
Jeppe Johansen
8f4173c54d
Add a number of optimizations.
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Don't do CSE restructuring when has full evaluation enabled.
git-svn-id: branches/laksen/riscv_new@39781 -
2018-09-20 20:27:58 +00:00
Jeppe Johansen
6d9a0fdc73
Added implementation of InstructionLoadsFromReg.
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Fixed spilling_get_operation_type_ref, no mem operation modifies ref registers.
git-svn-id: branches/laksen/riscv_new@39487 -
2018-07-22 18:38:07 +00:00
Jeppe Johansen
a906feb05e
Fixed bug in peephole optimizer.
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git-svn-id: branches/laksen/riscv_new@39486 -
2018-07-22 16:58:10 +00:00
Jeppe Johansen
054bf32f1f
Add RV64GC cpu type.
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Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.
git-svn-id: branches/laksen/riscv_new@39481 -
2018-07-21 22:34:42 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
