psub.pas: Use new fpc_compiler_has_fixup_jmps conditional.
mips/aasmcpu.pas: MIPS specific fixup_jmps function,
The insttruction distance calculation is not exact as
some pseudo-instruction can be expanded to a variable number of real instructions
real calculation would only be possible if we first
convert pseudo-instuctions to real instructions before calling fixup_jmps.
ncgutil.pas: Revert commit r21791
ncgcon.pas: Revert commit r21786
mips/cgcpu.pas: Partial revert of commit r21798, no need to always use A_J,
as fixup_jmps now handles out of range branches.
git-svn-id: trunk@21822 -
The old code forced dst and src to be the same, which is highly x86
specific and creates bad register utilization on other architectures
like arm.
The new version will use more imaginary registers, allowing the register
allocator to do a better job.
I've merged second_sar and second_rox into a single procedure
second_rox_sar because they were very similar.
git-svn-id: trunk@21809 -
RegInOp did not check for a register beeing part of a shifterop
(op.shifterop^.rs) which could result in trashed registers (But that did
not seem to happen yet anyway).
I've also implemented support for top_regset, but it is currently not
generated outside of proc_entry/proc_exit anyway.
git-svn-id: trunk@21808 -
This removes the duplications in a_op_reg_reg_reg_checkoverflow.
OP_ROL stays seperate because it needs some special treatment again.
The code for OP_ROL was changed, previously it generated:
mov tempreg, #32
sub src1, tempreg, src1
mov dst, src2, ror src1
This would trash src1, which MIGHT be a problem, but i'm not totally
sure. But the mov/sub was replaced with rsb, so the new code looks like
this.
rsb tempreg, src1, #32
mov dst, src2, ror tempreg
If src1 gets freed afterwards the regallocator should be able to change
that into:
rsb src1, src1, #32
mov dst, src2, ror src1
git-svn-id: trunk@21804 -
The previous code was full with duplicated code, this new version just
maps the OP_* to the correct SM_* and does some special handling for
OP_ROL which is done via OP_ROR.
git-svn-id: trunk@21801 -
symtable.pas, searchsym_in_class:
* if we found a helper method that has overload defined we should not forget the symbol as there can be a case that no method with that name is defined in the extended class hierarchy
symtable.pas, searchsym_in_record:
* analogous to the above
+ added test given in the issue
+ added analogous test for record helpers
git-svn-id: trunk@21764 -
pgenutil.pas, specialization_init:
* don't add implementation units of the generic's unit to the symtable stack if we are specializing in a different unit (thus the generic needs to be defined in the interface section) as there is the possibility that the globalsymtable of an implementation unit is not yet defined if the specialization unit is used in the interface section of an implementation unit
git-svn-id: trunk@21763 -
This fixes 64bit shifts on arm with a constant shift value of 0.
The old code would have emitted something like this
mov r0, r0, lsl #32
as 32 is an invalid shift value (and would be wrong anyway) the
assembler declined to assemble the produced source.
The new code will just not emit any code for a shift value of 0.
tests/test/tint642.pp now tests shl/shr 0 on 64 bit values.
tests/webtbs/tw22326.pp is also added as an additional test.
git-svn-id: trunk@21746 -
* Changed type of symbols created by link script from AT_FUNCTION to AT_DATA. This isn't significant for COFF, but matters for ELF targets.
* Changed alignment of .gnu_debuglink section from 0 to 1, this matches behavior of ld.
git-svn-id: trunk@21741 -
with the enum instance corresponding to ordinal 0 in JVM constructors,
because a virtual method called by a parent constructor may already
have assigned a different value (see tests/test/jvm/tenum2.pp). This
will result in null pointer exceptions when using such fields without
first explicitly assigning a value to them though.
The old behaviour can be restored with the new -CTenumfieldinit command
line parameter
git-svn-id: trunk@21736 -
