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749 Commits

Author SHA1 Message Date
Jonas Maebe
555634b755 * (re)set upper bits of register when appropriate for all operations in 
a_op_reg_reg() (except for NOT, which was already handled correctly)
    + test

git-svn-id: trunk@25840 -
 2013-10-22 07:41:52 +00:00
Jonas Maebe
10ae87f11c * fixed LdrLdr2LdrMov optimisation in case the first and second ldr have 
a different size (disable it in that case) + test

git-svn-id: trunk@25778 -
 2013-10-14 12:49:34 +00:00
Jonas Maebe
5276159e77 * correct ofset for saving floating point registers + explanation behind 
the calculation (fixes make cycle on ARMHF)

git-svn-id: trunk@25777 -
 2013-10-14 12:49:31 +00:00
Jonas Maebe
31a3122b91 * fixed LsrAnd2Lsr test by replacing the existing buggy check with comparing 
the outcome of the original and the optimised sequence and seeing whether
    it's same + test

git-svn-id: trunk@25776 -
 2013-10-14 12:49:28 +00:00
sergei
a5ae26da7e * Moved SkipEntryExitMarker method from ARM optimizer to the base one, since it is not target-dependent. Now it can be reused by other targets. 
git-svn-id: trunk@25738 -
 2013-10-10 21:12:49 +00:00
svenbarth
c48d572996 Implement support for saving and restoring address registers. 
cgobj.pas, tcg:
  * g_save_registers: add the amount of used address registers to size as well
  * g_save_registers: save all used address registers
  * g_restore_registers: restore all stored address registers
m68k/cpubase.pas:
  * rename saved_standard_address_registers to saved_address_registers
all other platform's cpubase.{inc,pas} (except alpha, ia64 and vis which are not up to date):
  * add a saved_address_registers variable with one entry of RS_INVALID

At least a "make fullcycle" did complete.

git-svn-id: trunk@25664 -
 2013-10-05 21:43:42 +00:00
florian
73e6af4864 + cpu flag CPUARM_HAS_THUMB_IDIV 
* test for CPUARM_HAS_THUMB_IDIV instead the CPU type when creating sdiv/udiv code

git-svn-id: trunk@25648 -
 2013-10-05 12:38:55 +00:00
florian
8fb7cf822b * unified internal errors 
git-svn-id: trunk@25647 -
 2013-10-05 12:37:46 +00:00
florian
e0f48b9f02 * calculate stack correction on exit correctly if stack parameters are passed 
git-svn-id: trunk@25427 -
 2013-09-05 21:40:33 +00:00
florian
36e6f99843 * fix tthumbcgarm.g_flags2reg, mov reg,#imm for thumb updates the flags 
git-svn-id: trunk@25426 -
 2013-09-05 21:40:30 +00:00
florian
e2ec3bbcb0 * do shifts for sign/zero extensions correctly 
git-svn-id: trunk@25418 -
 2013-09-04 21:00:46 +00:00
Károly Balogh
2c49af3191 added missing closing parentheses 
git-svn-id: trunk@25413 -
 2013-09-04 14:56:53 +00:00
florian
333e84202f * fixed a_load_reg_reg for thumb 
git-svn-id: trunk@25408 -
 2013-09-03 21:11:02 +00:00
florian
7ef37b5d2a * PLD is not supported by thumb 
git-svn-id: trunk@25407 -
 2013-09-03 21:09:41 +00:00
florian
cb1f38b0af * strd/ldrd are not supported by thumb 
git-svn-id: trunk@25406 -
 2013-09-03 21:09:13 +00:00
Károly Balogh
86cb4d0c12 use a TSuperRegister instead of an aint 
git-svn-id: trunk@25383 -
 2013-08-28 12:58:29 +00:00
Károly Balogh
c677f1fd69 trying harder to follow the code style (no functional changes) 
git-svn-id: trunk@25382 -
 2013-08-28 11:25:15 +00:00
Károly Balogh
25619d4991 removed the const-in-the-left internalerror 
git-svn-id: trunk@25380 -
 2013-08-27 16:18:53 +00:00
Károly Balogh
cb4d01627f save an extra reg if it's required to keep 64bit stack alignment on ARM 
git-svn-id: trunk@25379 -
 2013-08-27 12:49:50 +00:00
masta
ff95d42216 Fix ShiftShift2Shift 1 ARM-peephole optimizer 
The previous code deleted the newly inserted instruction instead of the
existing one, which obviously broke code.

Assembly:
  mov r0, r0, lsr #23
  mov r0, r0, lsr #23

transformed into:
  mov r0, r0, lsr #23

expected was:
  mov r0, #0

The problem only shows up in the very unlikely case of two LSR/ASR or
two LSL following on each other and having a total shift of more than 31
bits.

This fixes test/opt/tarmshift.pp

I've also removed the {%norun} directive from tarmshift.pp as this test
does only make sense when it also runs.

git-svn-id: trunk@25374 -
 2013-08-26 17:41:54 +00:00
florian
d4968e054b + arm: tsettings.instructionset 
* the selected instruction set is now independent from the cpu type: e.g. armv7-a can perfectly execute thumb(2) code

git-svn-id: trunk@25370 -
 2013-08-25 21:56:12 +00:00
florian
7cef301e84 * disable optimization LdrbAnd2Ldrb for arm thumb as it is currently done 
git-svn-id: trunk@25356 -
 2013-08-23 18:41:26 +00:00
florian
f34bee1df7 * arm thumb does not support ror reg1,reg2,#imm 
git-svn-id: trunk@25355 -
 2013-08-23 18:41:24 +00:00
florian
950194678a * handle jump tables correctly when inserting constant pools on arm thumb 
git-svn-id: trunk@25354 -
 2013-08-23 18:41:21 +00:00
Károly Balogh
6591a24bd3 removed some code which must never be called, added an internalerror() instead 
git-svn-id: trunk@25352 -
 2013-08-23 15:58:37 +00:00
florian
e514e84c83 * first_moddivint should not change the return type if div/mul/add is used 
* use create_internal when creating internally add nodes

git-svn-id: trunk@25351 -
 2013-08-23 15:23:00 +00:00
florian
3ebe708574 * do not use r13/r15 for certain data processing operations 
* correct OP_AND with certain types of constants

git-svn-id: trunk@25350 -
 2013-08-23 15:22:58 +00:00
florian
2fe48077b2 * using r13 and r15 is on arm thumb2 also forbidden under certain conditions for the instructions A_SUB,A_AND,A_BIC,A_EOR 
git-svn-id: trunk@25349 -
 2013-08-23 15:22:55 +00:00
florian
d5ddf39f73 * do not do the RedundantMovProcess optimization when the involved registers are r13 or r15 and if the target is arm thumb(2) 
git-svn-id: trunk@25348 -
 2013-08-23 15:22:53 +00:00
florian
b4c7b40049 * do not split statements following A_IT* instructions on arm thumb2 when inserting constant pools 
git-svn-id: trunk@25347 -
 2013-08-23 15:22:51 +00:00
florian
8884f1c0bf * arm thumb2 supports only left shifted index registers up to 3 bits 
git-svn-id: trunk@25346 -
 2013-08-23 15:22:49 +00:00
florian
6df2917d93 * fix spilling of vfp instructions 
* spelling mistake fixed

git-svn-id: trunk@25345 -
 2013-08-23 15:22:46 +00:00
florian
c350c3a5e4 * arm thumb2 does not understand tst reg1,reg2,lsl reg3 
git-svn-id: trunk@25344 -
 2013-08-23 15:22:44 +00:00
florian
bb73a2891b * prevent generation of mul/mla statements with illegal registers 
git-svn-id: trunk@25343 -
 2013-08-23 15:22:41 +00:00
Jonas Maebe
4ec9ec2009 + PIC support for Darwin/ARM: 
o does not use GOT
   o enabled by default like for other Darwin platforms
  - removed Darwin/ARM call stub support: no longer needed with current
    Xcode versions (at least Xcode 4.2+), and we didn't support PIC
    in them yet

git-svn-id: trunk@25325 -
 2013-08-22 08:14:24 +00:00
Jonas Maebe
8ffb704b8c * don't split address labels from the instruction they belong with when 
rescheduling (needed for GOT-less PIC)

git-svn-id: trunk@25324 -
 2013-08-22 08:14:18 +00:00
Jonas Maebe
b31e5c2536 + PIC support for ARM jump tables (only for plain ARM right now, not 
yet for thumb/thumb2)

git-svn-id: trunk@25323 -
 2013-08-21 22:28:24 +00:00
florian
6606955b88 + basic support for pic on arm-linux 
git-svn-id: trunk@25297 -
 2013-08-19 21:35:37 +00:00
florian
2806947a8f + FindRegAllocBackward 
* search reg. allocations backward in RemoveSuperfluousMove because the changed instruction could be the first one in a list

git-svn-id: trunk@25289 -
 2013-08-18 18:56:56 +00:00
Jonas Maebe
57cdd8c106 * set symbol type/binding of data referred by ppc and arm/darwin stubs (part 
of r25264, fixes internalerror 2013081601 after r25266)

git-svn-id: trunk@25275 -
 2013-08-17 16:26:37 +00:00
Jonas Maebe
3b9b6a0cd7 * explicitly define the asmsymbols for Darwin call stubs as local 
git-svn-id: trunk@25264 -
 2013-08-16 10:07:46 +00:00
Károly Balogh
614afca755 ARM: try to inline 64bit multiplication for the most common cases instead of calling FPC_MUL_ helpers (results in 5-10x speedup) 
git-svn-id: trunk@25189 -
 2013-07-30 14:40:50 +00:00
florian
6f5bcaae2b * UMUL et al. have only register restrictions on arm below v6 
git-svn-id: trunk@25171 -
 2013-07-24 20:18:12 +00:00
Jeppe Johansen
d89b9a4311 Add support in ARM assembler reader for ldr reg, =literal syntax 
git-svn-id: trunk@25157 -
 2013-07-21 16:06:57 +00:00
Jeppe Johansen
fdcc68cfd7 Disabled preindex/postindexed peephole optimizations for Thumb and Thumb2 
git-svn-id: trunk@25156 -
 2013-07-21 14:21:16 +00:00
Jeppe Johansen
f3273fa87d Optimize Add/Sub+Ldr/Str by using preindexed references 
git-svn-id: trunk@24789 -
 2013-06-02 21:51:12 +00:00
Jeppe Johansen
2d823452b7 The scheduler pass of the ARM optimizer left markers in the instruction list, which could prevent further peephole optimizations 
git-svn-id: trunk@24781 -
 2013-06-02 16:37:41 +00:00
Jeppe Johansen
570b40faed Signed modulus by 2 on ARM with no division is optimized to a series of instructions instead of calling fpc_mod_longint. 
An ASR is removed from signed division by 2.

git-svn-id: trunk@24778 -
 2013-06-02 14:44:06 +00:00
Jonas Maebe
9938169d2c * don't use the paracgsize in get_paraloc_def(), because it generally 
contains the tcgsize of the entire parameter rather than only of
    what is left (-> calculate it from the remaining parameter length)

git-svn-id: trunk@24776 -
 2013-06-02 14:05:07 +00:00
Jonas Maebe
7566ddcc8f * add a tdef to each parameter location and set it for all target 
backends (not yet used, will be used in high level code generator)

git-svn-id: trunk@24761 -
 2013-06-02 10:24:02 +00:00