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59,354 Commits 100 Branches 75 Tags 302 MiB
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Commit Graph

349 Commits

Author SHA1 Message Date
svenbarth
921e73ab0c + add compiler support for the Z80 MSX-DOS target 
git-svn-id: trunk@45596 -
 2020-06-06 17:16:20 +00:00
svenbarth
b2d6c36e70 + add support for DEFB and DEFW directives to the internal assembler reader 
git-svn-id: trunk@45591 -
 2020-06-06 17:15:53 +00:00
nickysn
996ab2feba * renamed some REL sections to follow a similar naming convention 
git-svn-id: trunk@45566 -
 2020-06-02 22:44:57 +00:00
nickysn
d88da03e7d * z80: use the JRJP pseudo instruction to generate shorter code (it is 
translated to JR wherever possible, otherwise to JP)

git-svn-id: trunk@45510 -
 2020-05-26 19:52:27 +00:00
nickysn
c49213c561 + Z80: implemented the JRJP pseudo instruction in the Z80 internal asm writer 
git-svn-id: trunk@45502 -
 2020-05-25 22:40:41 +00:00
nickysn
195e7e0918 * translate jrjp to jp in the sdcc-sdasz80 asm writer 
git-svn-id: trunk@45498 -
 2020-05-25 16:29:31 +00:00
nickysn
f71b6f341b + added JRJP to various instruction lists 
git-svn-id: trunk@45497 -
 2020-05-25 16:12:06 +00:00
nickysn
c5d04d1a54 + Z80: added the JRJP pseudo instruction 
git-svn-id: trunk@45496 -
 2020-05-25 15:53:51 +00:00
nickysn
56632b720c + Z80: handle the flags register in TAoptBaseCpu.RegModifiedByInstruction 
git-svn-id: trunk@45452 -
 2020-05-20 21:21:26 +00:00
nickysn
88b6bbe6cc * compilation fixed after r45450 
git-svn-id: trunk@45451 -
 2020-05-20 21:02:46 +00:00
nickysn
cc47a49c81 + Z80: handle all instructions that modify registers, that are not an operand in TAoptBaseCpu.RegModifiedByInstruction 
git-svn-id: trunk@45450 -
 2020-05-20 20:57:59 +00:00
nickysn
2507c1ace6 * Reg1ReadDependsOnReg2 moved to TAoptBaseCpu 
* use Reg1ReadDependsOnReg2 in TAoptBaseCpu.RegModifiedByInstruction to handle properly Z80 subregisters

git-svn-id: trunk@45449 -
 2020-05-20 20:20:10 +00:00
nickysn
edcc14a5ce * Z80: JR can be both conditional and uncoditional jump, just like JP 
git-svn-id: trunk@45411 -
 2020-05-17 23:38:23 +00:00
nickysn
13028db5a4 - z80: disable regvars, because they don't work 
git-svn-id: trunk@45402 -
 2020-05-17 14:38:57 +00:00
nickysn
63af4e173d + z80: handle all instructions in TCpuAsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@45391 -
 2020-05-16 20:33:44 +00:00
nickysn
5502d6cc58 + Z80: report the flags usage for all the remaining instructions in TCpuAsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@45390 -
 2020-05-16 19:58:37 +00:00
nickysn
f0edd62b88 + Z80: report flags register information in TCpuAsmOptimizer.RegLoadedWithNewValue for 16-bit ADD,ADC,SBC,INC and DEC 
git-svn-id: trunk@45373 -
 2020-05-16 00:03:54 +00:00
nickysn
37b607143a + handle the flags register bits for many Z80 instructions in TCpuAsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@45366 -
 2020-05-14 22:44:48 +00:00
nickysn
4beb4bf8b2 + Z80: support the flags subregisters in the registers_interfere function 
git-svn-id: trunk@45347 -
 2020-05-12 01:58:10 +00:00
nickysn
c6c834949f + Z80: support all the flags subregisters in super_registers_equal 
git-svn-id: trunk@45346 -
 2020-05-12 01:47:58 +00:00
nickysn
fe12026959 + support the LD instruction in TCpuAsmOptimizer.RegLoadedWithNewValue 
git-svn-id: trunk@45345 -
 2020-05-11 23:55:23 +00:00
nickysn
bb4d7a7a50 + Z80: implemented TCpuAsmOptimizer.InstructionLoadsFromReg 
git-svn-id: trunk@45344 -
 2020-05-11 22:24:20 +00:00
nickysn
4abc498f2f + added the Z80 individual flag bits as subregisters 
git-svn-id: trunk@45342 -
 2020-05-11 19:17:31 +00:00
nickysn
4263ff44c1 + Z80: added a registers_interfere helper function 
git-svn-id: trunk@45338 -
 2020-05-11 15:29:42 +00:00
nickysn
5947adcd7b + added a correct implementation of TAOptBase.SuperRegistersEqual for the Z80 
git-svn-id: trunk@45337 -
 2020-05-11 14:21:26 +00:00
nickysn
06a728df24 + added the alternate Z80 register pairs BC', DE' and HL' 
git-svn-id: trunk@45333 -
 2020-05-11 04:23:02 +00:00
nickysn
9ce97e6ba5 + also recognize alternate registers in the Z80 inline asm scanner. This allows 
the "EX AF,AF'" instruction to be accepted and assembled as well.

git-svn-id: trunk@45332 -
 2020-05-11 00:55:32 +00:00
nickysn
b581751ef3 - cleaned up some x86-specific code from the Z80 inline asm reader 
git-svn-id: trunk@45331 -
 2020-05-11 00:46:24 +00:00
nickysn
75ce122d36 - removed commented out writeln 
git-svn-id: trunk@45290 -
 2020-05-06 03:24:15 +00:00
nickysn
bface9fd94 - reverted previous commit, since it was incorrect 
git-svn-id: trunk@45287 -
 2020-05-06 00:44:35 +00:00
nickysn
0caba1e84d + added internal error in taicpu.gencode.WriteNN to catch unhandled asm instructions 
git-svn-id: trunk@45286 -
 2020-05-06 00:38:55 +00:00
nickysn
0d402a1341 + support signed 8-bit immediate constants in the Z80 internal asm writer as well 
git-svn-id: trunk@45284 -
 2020-05-06 00:13:10 +00:00
nickysn
11a7b8592f + support instructions like BIT, SET and RES in the Z80 internal asm writer 
git-svn-id: trunk@45283 -
 2020-05-06 00:10:17 +00:00
nickysn
6764056eff + support the 'in A,(n)' and 'out (n),A' instrunction in the Z80 internal asm writer 
git-svn-id: trunk@45282 -
 2020-05-05 23:58:54 +00:00
nickysn
c81f433795 + Z80: support conditional JR 
git-svn-id: trunk@45281 -
 2020-05-05 23:49:41 +00:00
nickysn
b164f5aa65 + support relative jumps in the Z80 internal asm writer 
git-svn-id: trunk@45280 -
 2020-05-05 23:42:09 +00:00
nickysn
0a09359906 + support the RST instruction in the Z80 internal asm writer 
git-svn-id: trunk@45279 -
 2020-05-05 23:30:44 +00:00
nickysn
43686720c3 + fix for conditional JP in the Z80 internal asm writer 
git-svn-id: trunk@45275 -
 2020-05-05 22:45:40 +00:00
nickysn
3e14eddaf6 + support conditional operations in the Z80 internal asm 
git-svn-id: trunk@45274 -
 2020-05-05 22:42:21 +00:00
nickysn
58d6d64fba + Z80 internal asm: support OT_REF_ADDR16 in taicpu.gencode.WrinteNN 
git-svn-id: trunk@45273 -
 2020-05-05 22:30:49 +00:00
nickysn
4fed57adc1 + lots of fixes to the Z80 internal asm writer 
git-svn-id: trunk@45272 -
 2020-05-05 22:18:44 +00:00
nickysn
3ab5acccb1 * the parameter of WriteWord should be word, not byte :) 
git-svn-id: trunk@45269 -
 2020-05-05 20:35:08 +00:00
nickysn
256597be58 + Z80 internal asm: produce correct opcodes for register operands 
git-svn-id: trunk@45250 -
 2020-05-04 02:17:30 +00:00
nickysn
90ee079cd1 + partial implementation of pass2 asm opcode generation for the Z80 internal asm writer 
git-svn-id: trunk@45249 -
 2020-05-04 01:27:44 +00:00
nickysn
5d2be4da1c * Z80: match both signed and unsigned 16-bit constants as OT_IMM16 in the asm instab lookup 
git-svn-id: trunk@45248 -
 2020-05-04 00:20:50 +00:00
nickysn
27e9dde81a + implemented pass1 (calcsize) of the instruction encoding for the Z80 internal asm 
git-svn-id: trunk@45247 -
 2020-05-04 00:14:28 +00:00
nickysn
19c1ecda54 + started work on the Z80 internal assembler 
git-svn-id: trunk@45191 -
 2020-04-30 14:27:48 +00:00
nickysn
9b1eebd333 + z80: add operand info to the result of taicpu.GetString, this makes the 
compiler produce nicer error messages, when it encounters an invalid
  instruction in inline asm code

git-svn-id: trunk@45187 -
 2020-04-30 00:17:29 +00:00
nickysn
34112c932c + handle OT_IMM8 and OT_IMM16 for getting symbol addresses in taicpu.Matches 
git-svn-id: trunk@45185 -
 2020-04-29 23:45:09 +00:00
nickysn
a79d12ae41 + handle OT_RELJMP8 in taicpu.Matches 
git-svn-id: trunk@45184 -
 2020-04-29 23:39:47 +00:00