Commit Graph

141 Commits

Author SHA1 Message Date
florian
046b148f5f * i386 and i8086 have an index register, so define cpurefshaveindexreg
git-svn-id: trunk@33540 -
2016-04-21 19:50:47 +00:00
pierre
885b0034c5 Allow use of stabs for 64-bit systems with -dUSE_STABS_64
git-svn-id: trunk@32185 -
2015-10-29 09:23:30 +00:00
Jonas Maebe
1c2bac7608 - removed FPC_HAS_VARSETS-related checks, FPC 2.6.4 has it
git-svn-id: trunk@31690 -
2015-09-15 11:51:42 +00:00
Jonas Maebe
3f9f498e0d - removed leftover alpha, ia64 and vis code
git-svn-id: trunk@31446 -
2015-08-28 22:31:29 +00:00
florian
ba1297b1ab + provide also 8 and 16 bit div/mod helper
* tmoddivnode.first_moddivint does not force a 32 bit helper, the used helper depends now on the resultdef type set by tmoddivnode.pass_typecheck

git-svn-id: trunk@31195 -
2015-07-05 20:16:50 +00:00
Jonas Maebe
3ab62fc36e * define TSymStr as ansistring for llvm, as its type definitions can be quite long
git-svn-id: trunk@30605 -
2015-04-15 18:29:44 +00:00
Jonas Maebe
67b8aceaee * synchronized with privatetrunk till r30095
git-svn-id: branches/hlcgllvm@30101 -
2015-03-05 20:32:15 +00:00
Jonas Maebe
41fba0c4f7 * switched to using the stack pointer as base register for the temp allocator
instead of the frame pointer register:
      1) we exactly know the offsets of the temps from the stack pointer
         after pass 1 (based on the require parameter stack size for called
         routines), while we don't know it for the frame pointer (it depends
         on the number of saved registers)
      2) temp offsets from the stack pointer are positive while those from
         the frame pointer are negative, and we can directly encode much
         bigger positive offsets in the instructions
   o move the stack pointer register to a virtual register in
     loadparentfpn, because many instructions cannot directly operate
     on/with the stack pointer
   o add the necessary register interference edges for the stack pointer
     register

git-svn-id: trunk@29938 -
2015-02-23 22:54:03 +00:00
Jonas Maebe
7949bebb8d * synchronised with r28168 of trunk
git-svn-id: branches/hlcgllvm@28169 -
2014-07-05 21:30:28 +00:00
sergei
0262514939 * m68k: Transform 32-bit div/mod nodes into helper calls during pass 1. This is consistent with the way other targets do it, and results in pretty much nicer code.
git-svn-id: trunk@28098 -
2014-06-28 13:28:01 +00:00
Jonas Maebe
bacd303208 * synchronized with trunk up to r27758
git-svn-id: branches/hlcgllvm@27779 -
2014-05-12 16:12:34 +00:00
sergei
96dd464bf2 * Moved fixup_jmps to target-specific classes for powerpc,powerpc64 and MIPS, cleaned out remaining $ifdef's. A slight functionality change is that fixup_jmps is now called before adding the procedure end symbol, not after, but that should not matter.
git-svn-id: trunk@27450 -
2014-04-02 14:17:23 +00:00
Jonas Maebe
e9268a0a14 * synchronised with trunk up till r26975
git-svn-id: branches/hlcgllvm@26976 -
2014-03-06 21:36:58 +00:00
yury
c58340f8dd * Enabled safecall for mips.
git-svn-id: trunk@26709 -
2014-02-07 14:12:33 +00:00
florian
e210d5f30e + cpu_capabilites for x86_64 and i386
* take advantage of bmi2 instruction rorx

git-svn-id: trunk@26482 -
2014-01-16 21:47:28 +00:00
Jonas Maebe
fd9b32f87d + defines for llvm targets
git-svn-id: branches/hlcgllvm@26053 -
2013-11-11 11:16:20 +00:00
florian
bbabb77ec9 * disable 32 bit operation optimization for powerpc64
git-svn-id: trunk@25979 -
2013-11-06 21:11:08 +00:00
svenbarth
6f5a648516 Improve the cpu type handling for M68k just in case we should branch 2.8.0 before I can start working on M68k again.
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.

fpcdefs.inc:
  + define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
  * check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
  - the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
  - tcputype: remove "cpu_coldfire"
  + tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
  + add "cpu_coldfire" constant which contains all Coldfire specific cpu types
  * adjust "cputypestr" and  "gascputypestr"
  + add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
  * adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
  * don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
  * adjusted check for Coldfire

git-svn-id: trunk@25457 -
2013-09-11 17:07:32 +00:00
florian
86c36995dd * i8086 has no 32 bit rol/ror support so disabled inlined ror/rol for now
git-svn-id: trunk@25237 -
2013-08-11 16:12:37 +00:00
sergei
404c3efa58 * MIPS: handle get_frame internally, so it sets pi_needs_stackframe flag on current procedure. This makes possible not to force pi_needs_stackframe on every procedure and thus omit saving/restoring $fp register when it is not necessary.
git-svn-id: trunk@25170 -
2013-07-24 15:25:12 +00:00
sergei
f80ce76a69 + MIPS: emulate "flags", i.e. support LOC_FLAGS location. This allows to generate differently optimized code for branching and for conversion to register, typically saving a register and instruction per compare.
git-svn-id: trunk@25131 -
2013-07-19 14:06:47 +00:00
sergei
87cfd86172 * Define SUPPORT_GET_FRAME for targets having "get_frame" as internal symbol (x86,arm and jvm, currently), removes need to enumerate these targets in every related conditional compilation directive and simplifies configuring this feature for other targets.
git-svn-id: trunk@24978 -
2013-06-26 11:03:24 +00:00
nickysn
0a8e008a0d + the ES register made volatile on i8086 as per the 16-bit x86 calling conventions
git-svn-id: trunk@24462 -
2013-05-07 14:27:21 +00:00
nickysn
f75ff8cc26 + enable the div helper for i8086
git-svn-id: branches/i8086@23880 -
2013-03-16 23:20:18 +00:00
nickysn
d72d496478 * enable cpuneedsmulhelper for the 32-bit multiplication
git-svn-id: branches/i8086@23796 -
2013-03-11 23:43:00 +00:00
nickysn
a9809323dc some more generic i8086 defines added
git-svn-id: branches/i8086@23712 -
2013-03-07 22:46:00 +00:00
Jonas Maebe
2dac1c445a - disabled Stabs support on 64 bit targets (mantis #23365)
* show a warning if an unsupported debug format is selected

git-svn-id: trunk@23056 -
2012-11-24 13:15:58 +00:00
florian
7089d1d638 + defines for aarch64 to configure the compiler
git-svn-id: trunk@22895 -
2012-10-31 21:51:04 +00:00
Jeppe Johansen
8b17a358e4 Remove all traces of the interrupt vector table generation mechanism
Clean up cpuinfo tables
Fixed ARMv7M bug(BLX <label> doesn't exist on that version)

git-svn-id: branches/laksen/arm-embedded@22579 -
2012-10-08 00:10:52 +00:00
pierre
f36c769c2f + Add SUPPORT_SAFECALL conditional
git-svn-id: trunk@22487 -
2012-09-27 15:56:20 +00:00
pierre
bc0c94c204 fpcdefs.inc: Set fpc_compiler_has_fixup_jmps for powerpcXX and mips CPUs.
psub.pas: Use new fpc_compiler_has_fixup_jmps conditional.
 mips/aasmcpu.pas: MIPS specific fixup_jmps function,
   The insttruction distance calculation is not exact as
   some pseudo-instruction can be expanded to a variable number of real instructions
   real calculation would only be possible if we first 
   convert pseudo-instuctions to real instructions before calling fixup_jmps.

 ncgutil.pas: Revert commit r21791
 ncgcon.pas: Revert commit r21786
 mips/cgcpu.pas: Partial revert of commit r21798, no need to always use A_J,
 as fixup_jmps now handles out of range branches.

git-svn-id: trunk@21822 -
2012-07-09 08:59:13 +00:00
pierre
23a3275291 * Define both mipseb and mips for non endian-little MIPS compiler
git-svn-id: trunk@21663 -
2012-06-20 16:11:00 +00:00
pierre
600dd162af Merge of rev21557 by Foxsen
Make macro MIPS/CPUMIPS/MIPS32 common for big endian and little endian mips processors
use MIPSEL* for little endian systems
use MIPSEB* for big endian systems

git-svn-id: trunk@21599 -
2012-06-13 22:25:38 +00:00
pierre
1e1e0f969e * Patch from Fuxin Zhang: remove cpuflags define for mips and mipsel CPUs
git-svn-id: trunk@21533 -
2012-06-07 23:08:18 +00:00
Jonas Maebe
aee5380ae0 * merged trunk up to r20882
o support for the new codepage-aware ansistrings in the jvm branch
   o empty ansistrings are now always represented by a nil pointer rather than
     by an empty string, because an empty string also has a code page which
     can confuse code (although this will make ansistrings harder to use
     in Java code)
   o more string helpers code shared between the general and jvm rtl
   o support for indexbyte/word in the jvm rtl (warning: first parameter
     is an open array rather than an untyped parameter there, so
     indexchar(pcharvar^,10,0) will be equivalent to
     indexchar[pcharvar^],10,0) there, which is different from what is
     intended; changing it to an untyped parameter wouldn't help though)
   o default() support is not yet complete
   o calling fpcres is currently broken due to limitations in
     sysutils.executeprocess() regarding handling unix quoting and
     the compiler using the same command lines for scripts and directly
     calling external programs
   o compiling the Java compiler currently requires adding ALLOW_WARNINGS=1
     to the make command line

git-svn-id: branches/jvmbackend@20887 -
2012-04-15 15:54:10 +00:00
Jonas Maebe
6ba8dc7146 + support for the ARM hard float EABI on Linux (patch by Peter Green):
o new eabihf (hard float) abi
   o vfpv3_d16 variant of VFP (default variant used by EABI assemblers: VFPv3
     with only 16 double registers instead of 32) and pass it to GNU as
   o make the odd numbered single precision floating point VFP registers
     available for explicit allocation for use by the calling convention
  * fixed copy/paste error in stdname of S30 register
  -> use -dFPC_ARMHF to create an ARM eabi hard float compiler
  (mantis #21554)

git-svn-id: trunk@20660 -
2012-03-29 20:50:09 +00:00
florian
2f5ce095ce * RefsHaveIndexReg -> cpurefshaveindexreg
* cpurefshaveindexreg defined properly in fpcdefs.inc

git-svn-id: trunk@20504 -
2012-03-10 19:43:52 +00:00
pierre
4a351f42fe Commit some MIPS changes
git-svn-id: trunk@20219 -
2012-02-02 23:43:52 +00:00
pierre
736299ffd9 Add ia64 define cpuXXXX series
git-svn-id: trunk@20123 -
2012-01-20 14:19:59 +00:00
Jonas Maebe
f7adaef12a * defined cpu32bit for mips
git-svn-id: trunk@19690 -
2011-11-25 21:12:04 +00:00
florian
c12a4989d0 + use cpurox define in the compiler for CPUs having internal ror/rol support
+ optimize (i shl x) or (i shr (bitsizeof(i)-x)) and friends into rol/ror(x,i)

git-svn-id: trunk@19635 -
2011-11-13 18:40:34 +00:00
florian
6b4a5c3cf6 * default arm-linux to linux eabi, oabi is basically dead
git-svn-id: trunk@19562 -
2011-10-30 21:33:21 +00:00
Jonas Maebe
ce88df680b + symansistr conditional define that, when activated, makes the symbol/
mangled name handling ansistring rather than pshortstring based (required
    for JVM target; little effect on speed, some extra memory usage)

git-svn-id: branches/jvmbackend@18597 -
2011-08-20 08:13:50 +00:00
Jonas Maebe
dc8df7fe79 * define cpu32bit for the JVM target (used by psystem to initialise
default integer types)
  * define CPUDEFINED in pp.pas if JVM is defined
  * initialise the fpu types and currency in psystem for the JVM target

  * set uinttype/sinttype to 32 bit types also for all cpu32bitaddr cpus
    by default (required for JVM, which has a 64 bit alu but 32 bit
    "addresses" -- an address takes up 1 stack slot, a 64 bit int two;
    also, array indices are limited to 32 bit)

git-svn-id: branches/jvmbackend@18296 -
2011-08-20 07:36:08 +00:00
Jonas Maebe
e3e4d365c8 * converted the parts of tcgloadnode.pass_generate_code() and
tcgassignmentnode.pass_generate_code() for simple symbols and
    for simple assignments from tcgobj to thlcgobj

git-svn-id: branches/jvmbackend@18283 -
2011-08-20 07:21:31 +00:00
pierre
4d50a95320 Use FPC_HAS_SYSTEMS_INTERRUPT_TABLE conditional
undefined for now as long as
  systems_interrupt_table set
  defined in systems unit is empty.
  This removes several warnings from compiler compilation.

git-svn-id: trunk@17871 -
2011-06-29 15:03:55 +00:00
pierre
33cb4b4a83 + generic_cpu defines fro ppudump
git-svn-id: trunk@17779 -
2011-06-20 21:44:18 +00:00
florian
d5455cf6ac + software multiplication support for OS_16,OS_S16,OS_32,OS_S32
git-svn-id: branches/avr@17020 -
2011-02-26 20:33:01 +00:00
florian
ca76476cfa * avr needs div helper
git-svn-id: trunk@17015 -
2011-02-26 20:14:18 +00:00
florian
26fbfaf5a7 + introduce the usage of asizeint/asizeuint for cpus with sizeof("alu")<>sizeof(pointer)
git-svn-id: trunk@17011 -
2011-02-26 20:10:03 +00:00