433 Commits

Author	SHA1	Message	Date
florian	d71f823373	* cleanup	2025-02-14 20:33:33 +01:00
florian	1802a8c493	+ apply OptPass1Data to variable shifting/rotating operations as well	2025-02-09 15:23:24 +01:00
florian	6cd75b75c3	* apply OptPass1Data to UDIV/SDIV as well	2025-02-09 10:41:39 +01:00
florian	09be204011	+ extend node_not_zero to take range types into account ... + aarch64: if no FPC_DIVBYZERO call is needed, div nodes do not generate calls	2025-02-09 10:26:10 +01:00
florian	bcaa58db01	* extend node_not_zero and make more use of it	2025-02-09 09:42:52 +01:00
florian	b2f6214b33	+ a_bit_scan_reg_reg gets a flag if src cannot be zero: this simplifies the generated code	2025-02-08 14:27:48 +01:00
Sven/Sarah Barth	8f37905609	* use a static data label for the case-label table on aarch64-win64 to avoid the linker discarding it	2024-11-22 17:57:02 +01:00
Sven/Sarah Barth	7b3efe6397	* on aarch64-win64 the case-labels are a list of 8-Byte aligned 8—Byte values, so adjust the alignment to avoid 2 32-bit loads	2024-11-22 17:56:11 +01:00
Sven/Sarah Barth	ad4fe174b1	* ensure that the section with the case-labels is 8-Byte aligned	2024-11-22 17:55:35 +01:00
Sven/Sarah Barth	0e39308416	* adjust comments to better match the situation with aarch64-win64 added to the mix	2024-11-22 17:54:57 +01:00
Sven/Sarah Barth	ee6bfa357a	* don't restore SP if we hadn't stored it originally	2024-11-10 22:00:45 +01:00
Sven/Sarah Barth	43d1036b3a	* fix encoding for save_freg_x	2024-11-10 22:00:45 +01:00
Sven/Sarah Barth	959804798c	* also restore SP on aarch64-win64 if registers had been stored	2024-11-10 22:00:45 +01:00
Sven/Sarah Barth	bb27442b19	* when removing the STP FP,LR and MOV FP,SP instructions, also remove the corresponding SEH directives if available	2024-11-08 23:30:16 +01:00
Sven/Sarah Barth	b67415d1a8	* don't generate pdata and xdata if there is neither a relevant prologue nor a handler	2024-11-08 23:30:15 +01:00
Sven/Sarah Barth	552ba93536	* on aarch64-win64 we need to restore the stack by first increasing the stackpointer and then restoring FP to match the code from the prologue	2024-11-08 18:18:12 +01:00
Sven/Sarah Barth	465537583b	* on aarch64-win64 do the assignment of the exception frame pointer only after the SEH prologue has been done as there is no SEH directive for assigning a register to FP	2024-11-08 18:17:12 +01:00
Sven/Sarah Barth	b7afb6237f	* fix encoding of ash_savereg and ash_savereg_x	2024-11-08 17:42:35 +01:00
Sven/Sarah Barth	0430e1bd1a	* pass all const record parameters on aarch64-win64 as references due to the habit of passing records as pointers by using the const modifier in the Windows unit	2024-11-08 16:47:39 +01:00
J. Gareth "Curious Kit" Moreton	2a50d5abf8	* ARMv7A / A64: Constant writes to memory merged to larger forms where possible	2024-11-03 15:02:51 +00:00
florian	4fea0e355e	+ apply OptPass1FData on FRINT*	2024-08-31 21:51:15 +01:00
florian	f81ce16d2a	+ AArch64: apply OptPass1FData also to FCSEL	2024-08-27 20:22:53 +01:00
florian	47d2395110	* set operand size properly for STX*	2024-07-08 21:54:05 +02:00
florian	b974e4a25f	* fix extension to 64 bit on aarch64, resolves #40576	2024-07-07 16:36:29 +02:00
florian	8cafafc3e6	+ add missing instructions	2024-07-05 21:06:21 +02:00
florian	6c50c02f7c	* bail out early in tcgaarch64.make_simple_ref if possible	2024-06-17 22:54:06 +02:00
J. Gareth "Curious Kit" Moreton	bf970b29f4	* arm / a64: TAsmNode debugging info is now output for ARM and AArch64	2024-05-30 20:04:11 +00:00
J. Gareth "Curious Kit" Moreton	605b21af8c	* a64: win64 implementation of jump table now ... uses 64-bit absolute references.	2024-05-27 06:31:15 +01:00
florian	f49da05633	* unified g_concatcopy_move	2024-05-15 22:52:24 +02:00
J. Gareth "Curious Kit" Moreton	88ab9576b1	* a64: Added "ABS" and "CTZ" mnemonics (CSSC instructions)	2024-04-21 09:06:16 +00:00
J. Gareth "Curious Kit" Moreton	1ba93085f7	* a64: Added DOTPROD and PAUTH support flags to relevant instruction sets (v8.4+ and v8.3+ respectively)	2024-04-21 09:06:16 +00:00
J. Gareth "Curious Kit" Moreton	bba4edb6d0	* a64: ARMv8.7 through ARMv8.9 have been added as AArch64 CPU types, along with support for the CSSC extension.	2024-04-21 09:06:16 +00:00
florian	9409ec6341	* workaround unsupported -march=...+pauth for some assembler/clang versions	2024-04-21 11:04:42 +02:00
J. Gareth "Curious Kit" Moreton	9ee1821622	* arm / a64: Extended the AND; CMP -> ANDS family of optimisations to catch BIC as well as AND	2024-04-20 12:55:47 +00:00
J. Gareth "Curious Kit" Moreton	77c86cafd0	* a64: Fixed bug where unsigned min/max inlines used a signed comparison	2024-03-26 14:18:31 +00:00
J. Gareth "Curious Kit" Moreton	81b7b80749	* Added support for 64-bit min/max intrinsics	2024-03-26 14:18:31 +00:00
J. Gareth "Curious Kit" Moreton	2b7df4237b	* nf_pass1_done, nf_error, nf_processing and nf_do_not_execute ... have been moved to a new "transientflags" node field that isn't stored in PPU files	2024-03-24 18:14:49 +00:00
J. Gareth "Curious Kit" Moreton	99851f22f5	* a64: New B -> RET peephole optimisation	2024-03-24 13:31:52 +00:00
florian	20f9b82543	* AArch64: overflow checking for abs ... * tabs adapted: also abs(longint) must overflow check on 64 bit platforms	2024-03-24 12:47:16 +01:00
florian	1fccfd3ee1	* AArch64: avoid false overflow error in case of -2^63+0	2024-03-24 12:36:02 +01:00
J. Gareth "Curious Kit" Moreton	a907eb49c9	* a64: Several secondary peephole optimizations that clean up CSEL instructions	2024-03-15 18:08:37 +00:00
J. Gareth "Curious Kit" Moreton	ef1cb852a8	* a64: New CSEL block optimisations ported over from x86 CMOV block optimisations	2024-03-15 18:08:37 +00:00
Michaël Van Canneyt	4e8b1cb97a	* Fixed signature of insert_init_final_table	2024-03-05 07:56:14 +00:00
florian	a71cc71585	+ function needs_check_for_fpu_exceptions to unify fpu exception handling	2024-02-13 17:42:21 +01:00
florian	3ed5a4a022	+ when calling FPC_THROWFPUEXCEPTION in a sub routine, pi_do_call must be set, fixed for aarch64	2024-02-12 23:25:35 +01:00
J. Gareth "Curious Kit" Moreton	bf29f2051c	* arm/a64: Added new TST post-peephole optimisation to replace previous AND/CMP/B(c) optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	b18c10d0d8	* arm/a64: New "OptPass2TST" routine to catch "TST; B.c; AND -> ANDS; B.c" optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	9f19f582c4	* arm/a64: New AND/CMP -> TST or ANDS optimisation	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	38d2f3d58c	* a64: Renamed OptPostCMP/And to PostPeepholeOptCMP/AND for internal consistency	2024-02-11 21:39:19 +00:00
J. Gareth "Curious Kit" Moreton	72081c803e	* a64: SkipAligns calls removed.	2023-12-29 14:17:08 +00:00