that itself, our LLVM code generator can't handle it, and if it did then
afterwards we would have to spill 90% of those register variables again
to make them SSA)
git-svn-id: trunk@44062 -
- Clean up handling of CPU/FPU type handling in RISCV.
- Do more fixes to get RISCV32 working.
- Fix most soft multiplication handling for generic RISCV code. Still missing a few.
- Add RISCV embedded targets.
git-svn-id: trunk@42335 -
Fix float loading.
Fix a number of small issues with wrong operand sizes.
Fixed concatcopy code generation.
Align jump table for case statements.
git-svn-id: branches/laksen/riscv_new@39481 -
