o added AArch64 regset parsing support in assembler reader, means that "{"
no longer starts comments there (like in the ARM assembler reader)
o added AArch64 indexed SIMD register support and removed old cg hacks
that worked around its absence
git-svn-id: trunk@47116 -
+ Added postfix parsing in tattreader.GetToken
- Removed all postfixed versions of OpCodes from the instruction list
+ Added all missing OpCodes from Xtensa ISA
* Changed branch OpCode to A_B, similar to ARM
+ Added missing branch condition flags BCI and BSI
* Updated existing compiler code that referred to the old postfixed instructions
+ Added prefix and postfix handling in TxtensaInstrWriter.WriteInstruction
* Updated TCPUAddNode.second_addfloat to specify .S postfix
* Updated tcpuunaryminusnode.second_float to specify .S postfix
+ Implemented prefix and postfix identification in txtensaattreader.is_asmopcode
* Adapted branch condition extraction to respect postfixes
* Changed itcpugas to call findreg_by_name_table from raatt.pas (same as issue #0037121, difficult to test these changes without including a fix for the register name search problem)
git-svn-id: trunk@45672 -
* allow -128 to 255 as a constant for instructions taking a byte sized constants (this is also what GNU As accepts), resolves#32039
git-svn-id: trunk@38316 -
* changed most of the variables in the assembler readers used to store constants from aint to tcgint
as aint has only the size of the accumular while some CPUs (AVR) allow larger constants in instructions
+ allow access to absolute symbols with address type in inline assembler
* allow absolute addresses in avr inline assembler
+ tests
git-svn-id: trunk@37411 -
directly in inline assembly: that's only possible if it's a register
parameter where the address of the record was passed (rather than the
record itself), or if a parameter has been explicitly typecasted in
Intel-style assembly using ".size"
git-svn-id: trunk@35959 -
it was AT_NONE, which is invalid and should never be used
* explicitly pass the correct value for all calls to those methods elsewhere
in the compiler
git-svn-id: trunk@34250 -
tasmdata.DefineAsmSymbol() and all routines that call it
o will be used to automatically generate AB_INDIRECT sybols when
necessary
git-svn-id: trunk@34164 -
Switched codegeneration of VFPv2 and VFPv3 to use UAL mnemonics and syntax.
Updated VFP code in RTL to use UAL syntax too.
Added preliminary ELF support for ARM.
Added support for linking of WinCE COFF files. Should work for with a standard ARMv4-I target.
git-svn-id: branches/laksen/armiw@29247 -
* generate add.w instead of add for thumb-2 in case one of the registers
is > r8
* add register interferences for the "add" instruction so the register
allocator can detect invalid instruction forms (even for assembler code)
* fixed error in thumb2.inc detected by the previous change
git-svn-id: trunk@16633 -
properties/behaviour of the equivalent of Extended in C (i.e., to
"long double" on i386 and x86_64 platforms that support a 10 byte
long double, and to "double" elsewhere)
git-svn-id: trunk@14912 -
a) cpu64bitaddr, which means that we are generating a compiler which
will generate code for targets with a 64 bit address space/abi
b) cpu64bitalu, which means that we are generating a compiler which
will generate code for a cpu with support for 64 bit integer
operations (possibly running in a 32 bit address space, depending
on the cpu64bitaddr define)
All cpus which had cpu64bit set now have both the above defines set,
and none of the 32 bit cpus have cpu64bitalu set (and none will
compile with it currently)
+ pint and puint types, similar to aint/aword (not pword because that
that conflicts with pword=^word)
* several changes from aint/aword to pint/pword
* some changes of tcgsize2size[OS_INT] to sizeof(pint)
git-svn-id: trunk@10320 -
