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bda163544a
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72 Commits

Author SHA1 Message Date
nickysn
bda163544a * tcg8086.g_flags2reg: restore the register back to the original size after the 
16-bit inc

git-svn-id: trunk@26337 -
 2013-12-31 13:15:30 +00:00
nickysn
fbd05c4e12 * Improved code generation in tcg8086.g_flags2reg for the case when target reg 
size is >=16-bit:
  o Generated code is now one instruction and one byte shorter.
  o No 8-bit subregisters are used, which reduces register pressure.

git-svn-id: trunk@26336 -
 2013-12-31 11:31:23 +00:00
nickysn
d57d982be7 * simpler handling of moves from a smaller to a larger cgsize in 
tcg8086.a_load_reg_ref, which additionally fixes the following issues:
  o The higher parts of the source register is no longer modified.
  o The source register's size is no longer modified with makeregsize.
  o Conversion from OS_S8 to a larger size is now supported.

git-svn-id: trunk@26335 -
 2013-12-31 00:33:37 +00:00
nickysn
5d0814016d * improvements and fixes in tcg8086.a_load_reg_reg and .a_load_ref_reg: 
o When expanding from a OS_8 to a 16-bit or 32-bit tcgsize, use the R_SUBH
    subregister to initialize the high 16 bits of the register to zero. This
    generates shorter and faster code, without increasing register
    interferences, because R_SUBH has the same register constraints on i8086 as
    R_SUBL, which is already used on the same imaginary register.
  o After performing operations on the 8-bit subparts of a register that was
    initially 16-bit, call makeregsize(OS_16) to notify the register allocator
    that the register is once again 16-bit.

git-svn-id: trunk@26328 -
 2013-12-30 21:20:10 +00:00
nickysn
6d48b32115 * fixes and improvements in tcg8086.a_load_reg_reg for the case when the src and 
dest are subregisters of the same superregister, but of different sizes:
   o Do not emit spurious moves from a register to the same register.
   o Correctly support the case when converting from 16-bit to 32-bit int.
     Previously it didn't work correctly, because in this particular case, due
     to the way the GetNextReg scheme works, we have reg1=reg2.

git-svn-id: trunk@26313 -
 2013-12-29 17:15:58 +00:00
nickysn
fdd36b4603 * on i8086 with regvars on, do not notify the register allocator of moves to BX. 
This fixes compilation of unit math (and the whole RTL) with regvars enabled.

git-svn-id: trunk@26282 -
 2013-12-25 12:19:21 +00:00
nickysn
8bfe2a56dd * optimized SAR by 31 to use only one SAR instruction in tcg8086.a_op_const_reg 
git-svn-id: trunk@25883 -
 2013-10-30 16:53:59 +00:00
nickysn
bfd31e7516 * optimizations in tcg8086.g_copyvaluepara_openarray: 
- when elesize=2, avoid the SHR CX,1 instruction
  - use rep movsw even for odd elesizes, unless cs_opt_size is set

git-svn-id: trunk@25829 -
 2013-10-19 15:07:55 +00:00
nickysn
ff9ce0d20d * tcg8086.g_copyvaluepara_openarray improvements: 
- use a_op_const_reg for the multiplication, instead of emitting directly
    instructions, which are 186+
  - avoid using IMUL twice, when the element size is not power of two
  - rm the system_i386_win32 leftovers

git-svn-id: trunk@25826 -
 2013-10-18 22:35:51 +00:00
nickysn
ef51c8c5a2 * fixed the interface wrapper code generation for virtual methods on i8086 in 
the medium memory model

git-svn-id: trunk@25817 -
 2013-10-18 12:11:50 +00:00
nickysn
116d3746ca * fixed the stack offset to the self parameter when generating an interface 
wrapper for a virtual method in tcg8086.g_intf_wrapper

git-svn-id: trunk@25816 -
 2013-10-18 10:56:04 +00:00
nickysn
83aa50de74 * emit a far jmp in the interface wrapper on i8086 in far code memory models 
git-svn-id: trunk@25812 -
 2013-10-17 21:55:45 +00:00
nickysn
814e1297ed * tcg8086.g_adjust_self_value fixed for far code memory models 
git-svn-id: trunk@25798 -
 2013-10-15 23:34:18 +00:00
nickysn
0aff18ac61 + implemented tcg64f8086.a_op64_ref_reg 
git-svn-id: trunk@25707 -
 2013-10-07 00:17:03 +00:00
nickysn
3cdbf9a805 + implemented tcg64f8086.a_op64_const_ref 
git-svn-id: trunk@25706 -
 2013-10-06 23:56:25 +00:00
nickysn
3bdd3d9a4e + optimization in tcg64f8086.a_op64_const_reg for OP_ADD and OP_SUB when the 
lowest 48, 32 or 16 bits of the constant are zeros

git-svn-id: trunk@25705 -
 2013-10-06 23:43:38 +00:00
nickysn
88c7ca96c5 + optimization in tcg8086.a_op_const_reg and .a_op_const_ref for 32-bit OP_ADD 
and OP_SUB when the low 16 bits of the const are 0

git-svn-id: trunk@25704 -
 2013-10-06 23:23:06 +00:00
nickysn
8f44e729cc * tcg8086.a_op_const_ref and .a_op_const_reg: when splitting a 32-bit OP_AND, 
OP_OR or OP_XOR operation into two 16-bit parts, call a_op_const_reg/ref
  recursively for the 16-bit parts, so certain optimizations can be done if the
  low or high 16-bit of the const are $ffff.

git-svn-id: trunk@25703 -
 2013-10-06 23:02:07 +00:00
nickysn
bd0585274e * tsettings.enablecld converted to a targetswitch ts_cld 
git-svn-id: trunk@25592 -
 2013-09-28 13:41:58 +00:00
nickysn
52fcc0a407 + added a new x86-specific compiler option 'enablecld', which controls whether 
the compiler should emit a CLD before using the x86 string instructions.

git-svn-id: trunk@25590 -
 2013-09-28 11:54:02 +00:00
nickysn
1f783f539c * emit a cld instruction before the rep movsXX in tcg8086.g_copyvaluepara_openarray as well 
git-svn-id: trunk@25556 -
 2013-09-24 20:09:11 +00:00
florian
11ff8a4ec1 + support register parameters with multiple locations 
git-svn-id: trunk@25238 -
 2013-08-11 16:12:39 +00:00
florian
57d4185d44 * allocate/deallocate cpu registers as late/early as possible, this gives the reg. allocator more flexibility 
git-svn-id: trunk@25229 -
 2013-08-08 20:55:45 +00:00
sergei
a21a20d559 + i8086-specific version of g_stackpointer_alloc. 
git-svn-id: trunk@25219 -
 2013-08-06 08:11:39 +00:00
nickysn
b81f0ab50d + implemented tcg8086.a_call_reg_far; very hacky, but still better than doing a near call, when it should be far 
git-svn-id: trunk@24856 -
 2013-06-09 22:16:40 +00:00
nickysn
604b7c9deb + added cg.a_call_ref_near and a_call_ref_far 
git-svn-id: trunk@24853 -
 2013-06-09 20:22:47 +00:00
nickysn
af54de6d56 + added tcg8086.a_call_name_far and .a_call_name_static_far; a_call_name and a_call_name_static overriden and call near or far depending on the memory model 
git-svn-id: trunk@24828 -
 2013-06-09 10:54:30 +00:00
nickysn
aa63efc27e * emit a far ret instruction in the exit code of far procedures 
git-svn-id: trunk@24817 -
 2013-06-08 20:40:50 +00:00
nickysn
e2241d97a2 * i8086 optimizations for 32-bit OP_SAR with const >= 16 
git-svn-id: trunk@24757 -
 2013-06-02 09:35:30 +00:00
nickysn
55a071692e * i8086 optimizations in op_const_reg for 32-bit OP_SHL and OP_SHR with const >= 16 
git-svn-id: trunk@24756 -
 2013-06-02 08:58:50 +00:00
nickysn
ec76b2cf40 * refactored the segment-in-integer-register reference support, so it's handled in make_simple_ref, instead of all over the place in the code generator 
git-svn-id: trunk@24752 -
 2013-06-01 22:18:09 +00:00
nickysn
e243b6b869 * never use the 66h prefix when pushing/popping segment registers on i8086, as the stack is aligned on 2 bytes there 
git-svn-id: trunk@24729 -
 2013-06-01 16:03:14 +00:00
nickysn
c2e3fb5918 + emit proper interrupt procedure entry/exit code on i8086 
git-svn-id: trunk@24728 -
 2013-06-01 15:50:11 +00:00
nickysn
c271594b4f + optimized implementation of 32-bit OP_SHL,OP_SHR and OP_SAR in tcg8086.a_op_const_reg 
git-svn-id: trunk@24660 -
 2013-05-31 11:03:36 +00:00
nickysn
06838be452 * fixed bug when passing a 'single' floating point type parameter via tcg8086.a_load_ref_cgpara 
git-svn-id: trunk@24592 -
 2013-05-25 13:37:24 +00:00
nickysn
27adafeecb + support moving from a shorter unsigned (sign extension not yet implemented) to a longer type in tcg8086.a_load_reg_ref 
git-svn-id: trunk@24589 -
 2013-05-25 12:05:02 +00:00
nickysn
3aeea835f9 + int register in treference.segment support in tcg8086.op_*ref* 
git-svn-id: trunk@24586 -
 2013-05-24 19:57:02 +00:00
florian
c1a1325a72 * reduce register pressure by allocating/deallocating registers as late/early as possible 
git-svn-id: trunk@24581 -
 2013-05-24 18:09:15 +00:00
nickysn
8b1e621665 * segment in int register support added also to tcg8086.a_load_reg_ref and .a_load_ref_reg 
git-svn-id: trunk@24570 -
 2013-05-24 14:46:40 +00:00
nickysn
9171c19601 * support int register in treference.segment in tcg8086.a_load_const_ref; this fixes farptr^:=const 
git-svn-id: trunk@24569 -
 2013-05-24 13:36:22 +00:00
nickysn
2557382815 - rm tcg8086.g_maybe_got_init as it's of no use for the i8086 
git-svn-id: trunk@24499 -
 2013-05-14 22:20:04 +00:00
nickysn
c4dd85a0eb + implemented tcg8086.a_op_reg_ref 
git-svn-id: trunk@24474 -
 2013-05-08 11:49:39 +00:00
nickysn
85b98671bd + implemented tcg8086.a_op_const_ref for op_add/and/or/sub/xor/move/none; this fixes inc(longint) among other things 
git-svn-id: trunk@24473 -
 2013-05-08 08:23:46 +00:00
nickysn
2d67a3169d * i8086 fixes in tcg8086.g_copyvaluepara_openarray 
git-svn-id: trunk@24467 -
 2013-05-07 22:34:26 +00:00
nickysn
502c2ffb94 * fixed tcg8086.a_load_reg_reg when doing an unsigned extension in the same superregister; this fixes the taddbool test 
git-svn-id: trunk@24466 -
 2013-05-07 21:20:40 +00:00
nickysn
5a4a3cbbc3 + implemented tcg8086.a_op_ref_reg; supports op_add/sub/xor/or/and 
git-svn-id: trunk@24464 -
 2013-05-07 19:19:55 +00:00
nickysn
4527fe8fa2 + added 8086 workaround for the 'imul reg,const' 186+ instruction. The compiler can now generate strict 8086/8088 code. 
git-svn-id: trunk@24404 -
 2013-05-01 19:18:12 +00:00
nickysn
8fddb1361b * got rid of push const also in tcg8086.a_loadaddr_ref_cgpara 
git-svn-id: trunk@24384 -
 2013-04-29 23:13:09 +00:00
nickysn
cfc3c6ec5d - cleanup tcg8086.a_loadaddr_ref_cgpara from unused code left over from i386 
git-svn-id: trunk@24383 -
 2013-04-29 23:08:12 +00:00
nickysn
76e3dd5cef * do not generate push const on the i8086, go through a register instead, unless it's 186+ 
git-svn-id: trunk@24381 -
 2013-04-29 22:29:26 +00:00