support (64-bit shl and shr are already inlined on i8086, regardless of the
presence of this define). As a side effect, this also improves the code,
generated for 64-bit divisions by power-of-2 constants on i8086.
git-svn-id: trunk@37019 -
per platform (currently only enabled for win32 and win64). Enabling it forces
code page conversion from the codepage of the .msg file to CP_ACP, before
writing the message to the console. Not enabling it keeps the previous
behaviour of not doing any kind of code page conversion for messages. This
feature should be tested and enabled per platform, because it requires code
page conversion support in the rtl (so it may require adding the appropriate
extra units, such as fpwidestring). When this feature is enabled for all
platforms, we can start keeping only one .msg file per language, because
having extra .msg files for different encodings for the same language becomes
redundant, since the compiler can do code page conversion to whatever code
page the console uses.
git-svn-id: trunk@36450 -
* tmoddivnode.first_moddivint does not force a 32 bit helper, the used helper depends now on the resultdef type set by tmoddivnode.pass_typecheck
git-svn-id: trunk@31195 -
instead of the frame pointer register:
1) we exactly know the offsets of the temps from the stack pointer
after pass 1 (based on the require parameter stack size for called
routines), while we don't know it for the frame pointer (it depends
on the number of saved registers)
2) temp offsets from the stack pointer are positive while those from
the frame pointer are negative, and we can directly encode much
bigger positive offsets in the instructions
o move the stack pointer register to a virtual register in
loadparentfpn, because many instructions cannot directly operate
on/with the stack pointer
o add the necessary register interference edges for the stack pointer
register
git-svn-id: trunk@29938 -
Therefor the cpu type (-Cp...) "coldfire" was split up into "isaa", "isaa+", "isab" and "isac". The Linux RTL can currently compiled for "68020", "isab" and "isac". For the other three Bcc.L must be handled differently (only Bcc.B/W supported) and for "68000" also EXT.L needs to be handled differently.
fpcdefs.inc:
+ define CPUCAPABILITIES if capabilities can be set for a certain CPU type (currently ARM, AVR and M68k)
options.pas:
* check for CPUCAPABILITIES instead of specific CPUs
assemble.pas:
- the handling of the CPU type is already done in m68k/ag68kgas.pas, Tm68kGNUAssembler.MakeCmdLine (and thereby already using the gascputypestr array!)
m68k/cpuinfo.pas:
- tcputype: remove "cpu_coldfire"
+ tcputype: add "cpu_isa_a", "cpu_isa_a_p", "cpu_isa_b" and "cpu_isa_c"
+ add "cpu_coldfire" constant which contains all Coldfire specific cpu types
* adjust "cputypestr" and "gascputypestr"
+ add tcpuflags and cpu_capabilities (DBRA restriction was checked with CPUCOLDFIRE, CAS/TAS will be needed for atomic operations and BRAL restriction was discovered during testing of new cpu types)
m68k/cgcpu.pas:
* adjust checks for "cpu_coldfire"
m68k/n68kadd.pas:
* don't use a BRA.L if it is not supported, but (at least for now) a BRA.W
aggas.pas:
* adjusted check for Coldfire
git-svn-id: trunk@25457 -
