Commit Graph

36 Commits

Author SHA1 Message Date
florian
d6e4af8279 + applied remaining patches of Torsten Grundke: adds gather instructions of avx2
git-svn-id: trunk@29745 -
2015-02-17 21:43:46 +00:00
florian
842e027a9f + prove of concept how FMA4 could be supported in inline assembler
git-svn-id: trunk@27214 -
2014-03-20 21:25:38 +00:00
florian
a79be2b05c + support for FMA instructions in inline assembler
+ extended avx test code with FMA

git-svn-id: trunk@27209 -
2014-03-20 20:06:56 +00:00
florian
aa107b914c * merged avx2 branch, developed by Torsten Grundke
git-svn-id: trunk@27200 -
2014-03-20 12:03:52 +00:00
florian
7028210817 + tzcnt assembler instruction
git-svn-id: trunk@26506 -
2014-01-18 12:11:50 +00:00
nickysn
0f69362edd - rm LEA reg,imm from x86ins.dat, as that's not a valid x86 instruction,
using it in inline asm causes an internal error and removing it didn't show
  any regressions after running the testsuite on i386-linux.

git-svn-id: trunk@25827 -
2013-10-18 23:26:58 +00:00
florian
9b6094a58c + added a few BMI instructions to see if they can be encoded
git-svn-id: trunk@24907 -
2013-06-16 09:35:21 +00:00
florian
283ff05127 * merged avx support in inline assembler developed by Torsten Grundke
git-svn-id: trunk@22568 -
2012-10-06 19:47:18 +00:00
florian
fc569e224d * handle all operand combinations of xadd, resolves #21146
git-svn-id: trunk@20177 -
2012-01-25 21:26:59 +00:00
florian
c011949765 + iretq for x86_64
git-svn-id: trunk@18273 -
2011-08-19 12:56:26 +00:00
florian
8308b46a94 + support for assembler instructions with four operands
+ support for insertq, resolves #19910

git-svn-id: trunk@18206 -
2011-08-14 16:46:35 +00:00
sergei
0231863fce + Added missing PMULLD instruction, part of Mantis #19910
git-svn-id: trunk@18106 -
2011-08-06 06:59:33 +00:00
sergei
354d0520b7 + x86 assembler: fixed MOVABS instruction (it is a x86_64-only subset of MOV with 8-byte immediates/offsets) and same-form encodings of MOV instruction.
git-svn-id: trunk@17666 -
2011-06-05 17:32:18 +00:00
sergei
504e0c6816 x86 assembler fixes:
* mkx86ins.pp: 'regmem' operand type in x86ins.dat must be converted to OT_RM_GPR, not OT_REGMEM. The latter does not restrict register type, allowing to use e.g. xmm registers in place of regular ones. 
* Finished 'movd' and 'movq', added some tests for them to tasm2.pp.

git-svn-id: trunk@17515 -
2011-05-20 20:39:35 +00:00
sergei
9e8a31193b x86 assembler:
* Optimized the opcode representation of movq and remaining 3DNow instructions
* Disallow immediates not fitting in 32 bits (Mantis #14685) + test
* Disallow push/pop with 32-bit operands in x86_64 + test

git-svn-id: trunk@17490 -
2011-05-17 20:06:12 +00:00
sergei
3b979fef6d * Re-commit r17437 after more testing and fixing aasmcpu.pp in r17449.
git-svn-id: trunk@17452 -
2011-05-14 11:04:52 +00:00
sergei
b257231203 * Revert r17437, it breaks builds with -O2 and builds on i386 (although -O- on x86_64 is ok).
git-svn-id: trunk@17439 -
2011-05-12 23:53:18 +00:00
sergei
1d81a1244b A big update of x86 instruction table, part 1 (mostly SIMD instructions):
* Using ot_mmxrm and ot_xmmrm operand types to match arguments, reduces number of required entries by half.
* Replaced all literal $66, $F2 and $F3 prefixes with control codes (\361, \334 and \333, respectively).
* Prefix control codes imply writing REX, so code \323 after them is no longer necessary, removed.
* Fixed technology flags (SSSE3, SSE4.1, SSE4.2)
- Removed codes \300 and \301 (intended to generate address size prefix). FPC does not support this feature (the prefix itself is generated, but process_ea rejects operands needing non-default address size). Probably we don't even need to support it. But if we do, a much simpler solution is check all operands, like today's NASM does.
* Fixed/added some instructions along the way, namely CRC32, UNPCKHPD, CMPNEQSD.

git-svn-id: trunk@17437 -
2011-05-12 19:49:19 +00:00
sergei
de8ae0f873 x86 assembler improvements:
* Simplified REX handling: instead of useless adjusting instruction length on every REX change, adjust it just once, based on the final REX value.
* Similar for omitting REX.W in certain instructions: set a flag and consider it once the entire instruction has been processed. This removes the requirement for \335 to be the last opcode.
* maybewriterex also after $F2 prefix
* Fixed behavior of codes \310 and \311 (16- and 32-bit address respectively), this is needed for a few fancy instructions like LOOP and JCXZ, which honor address-size prefix instead of REX.
+ control code \361 for $66 prefix
+ IF_SSSE3, IF_SSE41, IF_SSE42 instruction flags (with dummy values)

x86/x86ins.dat:
* replaced literal $67 prefixes with \310 or \311
* marked encodings containing code \310 as NOX86_64
* replaced literal $48 prefixes with \326

git-svn-id: trunk@17433 -
2011-05-12 13:09:51 +00:00
sergei
6739cec2b9 * Flagged with NOX86_64 instructions/encodings that are invalid in 64-bit mode.
* AESKEYGENASSIST is not ATT-specific name, it is used by Intel-style assemblers as well. Also updated tests/test/taes1.pp to reflect the change.
+ Added SCASQ, resolves #16730 (other opcodes mentioned in that report were added/fixed earlier)

git-svn-id: trunk@17431 -
2011-05-11 15:50:59 +00:00
florian
9279c6955e * support for SSSE3, SSE4,1, SSE4.2, AES instructions set by Emelyanov Roman, resolves #18527
+ test for aes support

git-svn-id: trunk@17256 -
2011-04-05 20:22:57 +00:00
Jonas Maebe
9273856e84 * disallow pusha*/popa* for x86_64 (mantis #14862)
* disallow pushfd/popfd for x86_64 (mantis #14862)
  * fixed assembling popfq with the internal assembler (it needs a rex.w
    prefisx, while pushfq doesn't)
  * changed the default opcode size of pushf/popf/pusha/popa in
    {$asmmode intel} from "native size" to 16 bit (compatible with Intel
    manuals and Kylix; in AT&T mode, the default size for those operations
    remains the native one)
  * changed pushf/popf in rtl/i386/* into pushfd/popfd because of the
    previous change

git-svn-id: trunk@15546 -
2010-07-10 16:22:46 +00:00
florian
447276c5bb * Jcc reads the flags, this was not in the dat yet, resolves #9278
* disabled 4 ops variant of insertq for now

git-svn-id: trunk@8133 -
2007-07-22 16:40:44 +00:00
florian
0e96eda236 + some sse4 instructions supported, resolves #9046
git-svn-id: trunk@7613 -
2007-06-09 19:45:06 +00:00
florian
2da51bce72 + cmpxchg16b
git-svn-id: trunk@6095 -
2007-01-21 11:04:19 +00:00
florian
6118c3e477 * fixed assembling of movd with 64 bit registers
* fixed passing of floats to c varargs

git-svn-id: trunk@5477 -
2006-11-25 20:32:32 +00:00
peter
d79df4c74a * 64bit support for shrd
git-svn-id: trunk@4541 -
2006-09-03 08:56:10 +00:00
florian
73e22f1919 * one byte inc/dec aren't allowed for x86_64
git-svn-id: trunk@3047 -
2006-03-26 20:27:02 +00:00
peter
eb725d4e44 Merged revisions 2908,2911,2913-2917 via svnmerge from
http://svn.freepascal.org/svn/fpc/branches/linker/compiler

........
r2908 | peter | 2006-03-13 13:35:48 +0100 (Mon, 13 Mar 2006) | 2 lines

  * merge trunk upto r2907

........
r2911 | peter | 2006-03-13 18:08:00 +0100 (Mon, 13 Mar 2006) | 2 lines

  * rename values to make room for operand size codes

........
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r2915 | peter | 2006-03-14 13:51:35 +0100 (Tue, 14 Mar 2006) | 2 lines

  * check aktcputype

........
r2916 | peter | 2006-03-14 15:06:32 +0100 (Tue, 14 Mar 2006) | 3 lines

  * merge 300 opcodes
  * more 64bit versions of opcodes

........
r2917 | peter | 2006-03-14 17:34:03 +0100 (Tue, 14 Mar 2006) | 3 lines

  * x86_64 tables
  * convert movq with normal registers to mov

........

git-svn-id: trunk@2931 -
2006-03-16 08:09:28 +00:00
florian
5ece7cbc2f * first part of x86-64 assembler
git-svn-id: trunk@2824 -
2006-03-09 22:05:16 +00:00
florian
db68fb68b4 * updated to nasm 0.98.39 and insns.dat Rev. 1.46
git-svn-id: trunk@836 -
2005-08-09 20:15:58 +00:00
florian
5df84f7222 * cvtxx2yy has now proper modification information
git-svn-id: trunk@757 -
2005-07-26 21:06:02 +00:00
florian
ebcb69478f * fixed a lot of stuff for fpu/mm register variables
git-svn-id: trunk@199 -
2005-06-04 21:23:15 +00:00
florian
588e2c38bf * dwarf branch merged 2004-06-16 20:07:06 +00:00
peter
e6929a1a32 * more x86_64 parameter fixes
* tparalocation.lochigh is now used to indicate if registerhigh
    is used and what the type is
2004-02-09 22:14:17 +00:00
florian
412072f71d * renamed instruction tables 2004-01-15 13:57:58 +00:00