alignment for each memory reference (mantis #12137, and
test/packages/fcl-registry/tregistry1.pp on sparc). This also
enables better code generation for packed records in many cases.
o several changes were made to the compiler to minimise the chances
of accidentally forgetting to set the alignment of memory references
in the future:
- reference_reset*() now has an extra alignment parameter
- location_reset() can now only be used for non LOC_(C)REFERENCE,
use location_reset_ref() for those (split the tloc enum so the
compiler can catch errors using range checking)
git-svn-id: trunk@12719 -
a) cpu64bitaddr, which means that we are generating a compiler which
will generate code for targets with a 64 bit address space/abi
b) cpu64bitalu, which means that we are generating a compiler which
will generate code for a cpu with support for 64 bit integer
operations (possibly running in a 32 bit address space, depending
on the cpu64bitaddr define)
All cpus which had cpu64bit set now have both the above defines set,
and none of the 32 bit cpus have cpu64bitalu set (and none will
compile with it currently)
+ pint and puint types, similar to aint/aword (not pword because that
that conflicts with pword=^word)
* several changes from aint/aword to pint/pword
* some changes of tcgsize2size[OS_INT] to sizeof(pint)
git-svn-id: trunk@10320 -
getjumplabel and added type para to getlabel for specific types
* moved lineinfo generation from assemble and aggas to dbgstabs
git-svn-id: trunk@1120 -
