Jeppe Johansen
02c3f328a2
- RISC-V: Share optimizations between 32 and 64-bit.
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git-svn-id: trunk@43934 -
2020-01-13 22:49:23 +00:00
pierre
fb33da5f41
Change parameter type to tcgint for is_imm12 and is_lui_imm functions to avoid range check errors
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git-svn-id: trunk@43609 -
2019-11-29 10:31:31 +00:00
florian
e1e8986462
* patch by J. Gareth Moreton, issue #36271 , part 3: support for the other architectures
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git-svn-id: trunk@43441 -
2019-11-10 16:11:40 +00:00
florian
69786ffe73
somehow committing went wrong, second part of last commit:
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+ AArch64: support for vX.8b/vX.16b register names
+ support for more than 256 registers in the register dat files
- removed totherregisterset
+ AArch64: use vmov to load immediates if possible
+ AArch64: use eor to clear mm registers
git-svn-id: trunk@42917 -
2019-09-03 21:07:33 +00:00
Jonas Maebe
1b6425176b
* synchronised with trunk till r42049
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git-svn-id: branches/debug_eh@42050 -
2019-05-12 18:44:05 +00:00
Jonas Maebe
281b3ad276
* fix case completeness and unreachable code warnings in compiler that would
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be introduced by the next commit
git-svn-id: trunk@42046 -
2019-05-12 14:29:03 +00:00
Jonas Maebe
8555ec1438
+ fpc_eh_return_data_regno() intrinsic to get the return register numbers
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for the Dwarf EH exception handler result
git-svn-id: branches/debug_eh@40070 -
2018-10-28 18:16:38 +00:00
pierre
92acd38f40
Fix for bug report #34380
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git-svn-id: trunk@39986 -
2018-10-18 20:21:54 +00:00
pierre
10f72ba2c8
Add missing TFenceFlags and TRoundingMode for riscv32
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git-svn-id: trunk@39818 -
2018-09-26 21:56:03 +00:00
florian
44150f43ac
* RISC-V 32 compilation fixed
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+ lazarus project file for the compiler added
git-svn-id: branches/laksen/riscv_new@39511 -
2018-07-26 19:18:47 +00:00
Jeppe Johansen
ceb38833f2
Added RiscV32/64 target, from a cleaned up version of branches/laksen/riscv/trunk.
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git-svn-id: branches/laksen/riscv_new@39474 -
2018-07-20 08:21:15 +00:00
