nickysn
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9309e2c42e
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* replace 'add/adc/sub/sbc/and/or/xor/cp orgreg' with 'add/adc/sub/sbc/and/or/xor/cp spilltemp' in
trgcpu.do_spill_replace
git-svn-id: branches/z80@44553 -
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2020-04-03 22:42:02 +00:00 |
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nickysn
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e43834c5d0
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* replace 'inc/dec orgreg' with 'inc/dec spilltemp' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44552 -
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2020-04-03 22:19:40 +00:00 |
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nickysn
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9d545342f8
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* replace 'add/adc/sub/sbc/and/or/xor/cp A,orgreg' with 'add/adc/sub/sbc/and/or/xor/cp A,spilltemp' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44537 -
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2020-04-03 20:05:42 +00:00 |
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nickysn
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a58bab4318
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+ replace 'ld orgreg,const' with 'ld spilltemp,const' in trgcpu.do_spill_replace
git-svn-id: branches/z80@44536 -
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2020-04-03 19:47:47 +00:00 |
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nickysn
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fe3f4a7447
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* fixes in trgcpu.do_spill_replace
git-svn-id: branches/z80@44535 -
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2020-04-03 19:41:39 +00:00 |
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nickysn
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8ceee70912
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* range check for spilltemp.offset in [-128..127], not [0..63] in trgcpu.do_spill_replace for Z80
git-svn-id: branches/z80@44534 -
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2020-04-03 19:32:10 +00:00 |
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nickysn
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8291d24b7f
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* fix comment
git-svn-id: branches/z80@44533 -
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2020-04-03 18:53:52 +00:00 |
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nickysn
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65efc495af
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+ add edges to disallow the use of the 8-bit subregisters of IX, IY and SP
git-svn-id: branches/z80@44513 -
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2020-04-02 02:28:14 +00:00 |
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florian
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e370e9ba15
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* register names fixed
git-svn-id: branches/z80@35670 -
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2017-03-27 20:30:51 +00:00 |
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florian
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ea52a23179
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+ skeleton for Z80 support
git-svn-id: branches/z80@35665 -
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2017-03-26 19:10:50 +00:00 |
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