{ $Id$ Copyright (c) 2000-2002 by Florian Klaempfl Code generation for add nodes on the SPARC This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. **************************************************************************** } unit ncpuadd; {$i fpcdefs.inc} interface uses node,ncgadd,cpubase; type tsparcaddnode = class(tcgaddnode) private function GetResFlags(unsigned:Boolean):TResFlags; function GetFPUResFlags:TResFlags; protected procedure second_addfloat;override; procedure second_cmpfloat;override; procedure second_cmpboolean;override; procedure second_cmpsmallset;override; procedure second_cmp64bit;override; procedure second_cmpordinal;override; end; implementation uses systems, cutils,verbose, paramgr, aasmtai,aasmcpu,defutil, cgbase,cgcpu, cpupara, ncon,nset,nadd, ncgutil,cgobj; {***************************************************************************** TSparcAddNode *****************************************************************************} function TSparcAddNode.GetResFlags(unsigned:Boolean):TResFlags; begin case NodeType of equaln: GetResFlags:=F_E; unequaln: GetResFlags:=F_NE; else if not(unsigned) then begin if nf_swaped in flags then case NodeType of ltn: GetResFlags:=F_G; lten: GetResFlags:=F_GE; gtn: GetResFlags:=F_L; gten: GetResFlags:=F_LE; end else case NodeType of ltn: GetResFlags:=F_L; lten: GetResFlags:=F_LE; gtn: GetResFlags:=F_G; gten: GetResFlags:=F_GE; end; end else begin if nf_swaped in Flags then case NodeType of ltn: GetResFlags:=F_A; lten: GetResFlags:=F_AE; gtn: GetResFlags:=F_B; gten: GetResFlags:=F_BE; end else case NodeType of ltn: GetResFlags:=F_B; lten: GetResFlags:=F_BE; gtn: GetResFlags:=F_A; gten: GetResFlags:=F_AE; end; end; end; end; function TSparcAddNode.GetFPUResFlags:TResFlags; begin case NodeType of equaln: result:=F_FE; unequaln: result:=F_FNE; else begin if nf_swaped in Flags then case NodeType of ltn: result:=F_FG; lten: result:=F_FGE; gtn: result:=F_FL; gten: result:=F_FLE; end else case NodeType of ltn: result:=F_FL; lten: result:=F_FLE; gtn: result:=F_FG; gten: result:=F_FGE; end; end; end; end; procedure tsparcaddnode.second_addfloat; var op : TAsmOp; begin pass_left_right; if (nf_swaped in flags) then swapleftright; { force fpureg as location, left right doesn't matter as both will be in a fpureg } location_force_fpureg(exprasmlist,left.location,true); location_force_fpureg(exprasmlist,right.location,(left.location.loc<>LOC_CFPUREGISTER)); location_reset(location,LOC_FPUREGISTER,def_cgsize(resulttype.def)); if left.location.loc<>LOC_CFPUREGISTER then location.register:=left.location.register else location.register:=right.location.register; case nodetype of addn : begin if location.size=OS_F64 then op:=A_FADDd else op:=A_FADDs; end; muln : begin if location.size=OS_F64 then op:=A_FMULd else op:=A_FMULs; end; subn : begin if location.size=OS_F64 then op:=A_FSUBd else op:=A_FSUBs; end; slashn : begin if location.size=OS_F64 then op:=A_FDIVd else op:=A_FDIVs; end; else internalerror(200306014); end; exprasmlist.concat(taicpu.op_reg_reg_reg(op, left.location.register,right.location.register,location.register)); end; procedure tsparcaddnode.second_cmpfloat; var op : tasmop; begin pass_left_right; if (nf_swaped in flags) then swapleftright; { force fpureg as location, left right doesn't matter as both will be in a fpureg } location_force_fpureg(exprasmlist,left.location,true); location_force_fpureg(exprasmlist,right.location,true); location_reset(location,LOC_FLAGS,OS_NO); location.resflags:=getfpuresflags; if left.location.size=OS_F64 then op:=A_FCMPd else op:=A_FCMPs; exprasmlist.concat(taicpu.op_reg_reg(op, left.location.register,right.location.register)); { Delay slot (can only contain integer operation) } exprasmlist.concat(taicpu.op_none(A_NOP)); end; procedure tsparcaddnode.second_cmpboolean; begin pass_left_right; force_reg_left_right(true,true); if right.location.loc = LOC_CONSTANT then tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,NR_G0) else exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0)); location_reset(location,LOC_FLAGS,OS_NO); location.resflags:=getresflags(true); end; procedure tsparcaddnode.second_cmpsmallset; begin pass_left_right; force_reg_left_right(true,true); if right.location.loc = LOC_CONSTANT then tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,NR_G0) else exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0)); location_reset(location,LOC_FLAGS,OS_NO); location.resflags:=getresflags(true); end; procedure tsparcaddnode.second_cmp64bit; var unsigned : boolean; procedure firstjmp64bitcmp; var oldnodetype : tnodetype; begin { the jump the sequence is a little bit hairy } case nodetype of ltn,gtn: begin cg.a_jmp_flags(exprasmlist,getresflags(unsigned),truelabel); { cheat a little bit for the negative test } toggleflag(nf_swaped); cg.a_jmp_flags(exprasmlist,getresflags(unsigned),falselabel); toggleflag(nf_swaped); end; lten,gten: begin oldnodetype:=nodetype; if nodetype=lten then nodetype:=ltn else nodetype:=gtn; cg.a_jmp_flags(exprasmlist,getresflags(unsigned),truelabel); { cheat for the negative test } if nodetype=ltn then nodetype:=gtn else nodetype:=ltn; cg.a_jmp_flags(exprasmlist,getresflags(unsigned),falselabel); nodetype:=oldnodetype; end; equaln: cg.a_jmp_flags(exprasmlist,F_NE,falselabel); unequaln: cg.a_jmp_flags(exprasmlist,F_NE,truelabel); end; end; procedure secondjmp64bitcmp; begin { the jump the sequence is a little bit hairy } case nodetype of ltn,gtn,lten,gten: begin { the comparisaion of the low dword have to be } { always unsigned! } cg.a_jmp_flags(exprasmlist,getresflags(true),truelabel); cg.a_jmp_always(exprasmlist,falselabel); end; equaln: begin cg.a_jmp_flags(exprasmlist,F_NE,falselabel); cg.a_jmp_always(exprasmlist,truelabel); end; unequaln: begin cg.a_jmp_flags(exprasmlist,F_NE,truelabel); cg.a_jmp_always(exprasmlist,falselabel); end; end; end; begin pass_left_right; force_reg_left_right(false,false); unsigned:=not(is_signed(left.resulttype.def)) or not(is_signed(right.resulttype.def)); location_reset(location,LOC_JUMP,OS_NO); exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reghi,right.location.register64.reghi)); firstjmp64bitcmp; exprasmlist.concat(taicpu.op_reg_reg(A_CMP,left.location.register64.reglo,right.location.register64.reglo)); secondjmp64bitcmp; end; procedure tsparcaddnode.second_cmpordinal; var unsigned : boolean; begin pass_left_right; force_reg_left_right(true,true); unsigned:=not(is_signed(left.resulttype.def)) or not(is_signed(right.resulttype.def)); if right.location.loc = LOC_CONSTANT then tcgsparc(cg).handle_reg_const_reg(exprasmlist,A_SUBcc,left.location.register,right.location.value,NR_G0) else exprasmlist.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0)); location_reset(location,LOC_FLAGS,OS_NO); location.resflags:=getresflags(unsigned); end; begin caddnode:=tsparcaddnode; end. { $Log$ Revision 1.27 2004-09-25 14:23:55 peter * ungetregister is now only used for cpuregisters, renamed to ungetcpuregister * renamed (get|unget)explicitregister(s) to ..cpuregister * removed location-release/reference_release Revision 1.26 2004/09/21 17:25:13 peter * paraloc branch merged Revision 1.25.4.1 2004/09/19 18:08:30 peter * int64 compare fixed Revision 1.25 2004/06/20 08:55:32 florian * logs truncated Revision 1.24 2004/06/16 20:07:10 florian * dwarf branch merged Revision 1.23.2.3 2004/06/02 16:07:52 peter * fixed 64bit compare Revision 1.23.2.2 2004/05/31 16:39:42 peter * add ungetiftemp in a few locations Revision 1.23.2.1 2004/05/30 17:54:14 florian + implemented cmp64bit * started to fix spilling * fixed int64 sub partially Revision 1.23 2004/01/12 22:11:39 peter * use localalign info for alignment for locals and temps * sparc fpu flags branching added * moved powerpc copy_valye_openarray to generic }