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315 lines
17 KiB
ObjectPascal
315 lines
17 KiB
ObjectPascal
{
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Copyright (c) 1998-2004 by Florian Klaempfl
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Basic Processor information
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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Unit cpuinfo;
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{$i fpcdefs.inc}
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Interface
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uses
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globtype;
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Type
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bestreal = extended;
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{$ifdef FPC_HAS_TYPE_EXTENDED}
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bestrealrec = TExtended80Rec;
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{$else}
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bestrealrec = TDoubleRec;
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{$endif}
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ts32real = single;
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ts64real = double;
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ts80real = extended;
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ts128real = type extended;
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ts64comp = type extended;
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pbestreal=^bestreal;
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{ possible supported processors for this target }
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tcputype =
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(cpu_none,
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cpu_386,
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cpu_486,
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cpu_Pentium,
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cpu_Pentium2,
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cpu_Pentium3,
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cpu_Pentium4,
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cpu_PentiumM,
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cpu_core_i,
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cpu_bobcat,
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cpu_core_avx,
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cpu_jaguar,
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cpu_piledriver,
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cpu_excavator,
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cpu_core_avx2,
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cpu_zen,
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cpu_zen2,
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cpu_skylake_x,
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cpu_icelake,
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cpu_icelake_client,
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cpu_icelake_server,
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cpu_zen3,
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cpu_zen4,
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cpu_zen5
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);
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tfputype =
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(fpu_none,
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// fpu_soft,
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fpu_x87,
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fpu_sse,
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fpu_sse2,
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fpu_sse3,
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fpu_ssse3,
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fpu_sse41,
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fpu_sse42,
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fpu_avx,
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fpu_fma,
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fpu_avx2,
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fpu_avx512f
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);
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tcontrollertype =
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(ct_none
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);
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tcontrollerdatatype = record
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controllertypestr, controllerunitstr: string[20];
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cputype: tcputype; fputype: tfputype;
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flashbase, flashsize, srambase, sramsize, eeprombase, eepromsize, bootbase, bootsize: dword;
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end;
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Const
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{ Is there support for dealing with multiple microcontrollers available }
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{ for this platform? }
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ControllerSupport = false;
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{ We know that there are fields after sramsize
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but we don't care about this warning }
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{$PUSH}
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{$WARN 3177 OFF}
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embedded_controllers : array [tcontrollertype] of tcontrollerdatatype =
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(
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(controllertypestr:''; controllerunitstr:''; cputype:cpu_none; fputype:fpu_none; flashbase:0; flashsize:0; srambase:0; sramsize:0));
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{$POP}
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{ calling conventions supported by the code generator }
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supported_calling_conventions : tproccalloptions = [
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pocall_internproc,
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pocall_register,
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pocall_safecall,
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pocall_stdcall,
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pocall_cdecl,
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pocall_cppdecl,
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pocall_far16,
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pocall_pascal,
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pocall_oldfpccall,
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pocall_mwpascal
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];
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cputypestr : array[tcputype] of string[16] = ('',
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'80386',
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'80486',
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'PENTIUM',
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'PENTIUM2',
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'PENTIUM3',
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'PENTIUM4',
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'PENTIUMM',
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'COREI',
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'BOBCAT',
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'COREAVX',
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'JAGUAR',
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'PILEDRIVER',
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'EXCAVATOR',
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'COREAVX2',
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'ZEN',
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'ZEN2',
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'SKYLAKE-X',
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'ICELAKE',
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'ICELAKE-CLIENT',
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'ICELAKE-SERVER',
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'ZEN3',
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'ZEN4',
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'ZEN5'
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);
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fputypestr : array[tfputype] of string[7] = (
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'NONE',
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// 'SOFT',
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'X87',
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'SSE',
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'SSE2',
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'SSE3',
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'SSSE3',
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'SSE41',
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'SSE42',
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'AVX',
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'FMA',
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'AVX2',
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'AVX512F'
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);
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sse_singlescalar = [fpu_sse..fpu_avx512f];
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sse_doublescalar = [fpu_sse2..fpu_avx512f];
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fpu_avx_instructionsets = [fpu_avx,fpu_fma,fpu_avx2,fpu_avx512f];
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{ Supported optimizations, only used for information }
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supported_optimizerswitches = genericlevel1optimizerswitches+
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genericlevel2optimizerswitches+
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genericlevel3optimizerswitches-
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{ no need to write info about those }
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[cs_opt_level1,cs_opt_level2,cs_opt_level3]+
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[cs_opt_peephole{$ifndef llvm},cs_opt_regvar{$endif},cs_opt_stackframe,
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cs_opt_loopunroll,cs_opt_uncertain,
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cs_opt_tailrecursion,cs_opt_nodecse,cs_useebp,
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cs_opt_reorder_fields,cs_opt_fastmath];
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level1optimizerswitches = genericlevel1optimizerswitches;
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level2optimizerswitches = genericlevel2optimizerswitches + level1optimizerswitches +
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[{$ifndef llvm}cs_opt_regvar,{$endif}cs_opt_stackframe,cs_opt_tailrecursion,cs_opt_nodecse,cs_opt_consts];
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level3optimizerswitches = genericlevel3optimizerswitches + level2optimizerswitches;
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level4optimizerswitches = genericlevel4optimizerswitches + level3optimizerswitches + [cs_useebp];
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type
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tcpuflags =
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(CPUX86_HAS_BTX, { Bit-test instructions (BT, BTC, BTR and BTS) are available }
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CPUX86_HAS_CMOV, { CMOVcc instructions are available }
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CPUX86_HAS_SSEUNIT, { SSE instructions are available }
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CPUX86_HAS_SSE2, { SSE2 instructions are available }
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CPUX86_HAS_SSSE3, { SSSE3 instructions are available }
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CPUX86_HAS_SSE4_1, { SSE 4.1 instructions are available }
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CPUX86_HAS_SSE4_2, { SSE 4.2 instructions are available }
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CPUX86_HAS_BMI1, { BMI1 instructions are available }
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CPUX86_HAS_BMI2, { BMI2 instructions are available }
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CPUX86_HAS_CMPXCHG16B, { CMPXCHG16B is available (not on i386, only for less ifdefs in the compiler }
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CPUX86_HAS_LAHF_SAHF, { LAHF/SAHF is available }
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CPUX86_HAS_POPCNT, { POPCNT is available }
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CPUX86_HAS_LZCNT, { LZCNT is available }
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CPUX86_HAS_MOVBE, { MOVBE is available }
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CPUX86_HAS_BSWAP, { BSWAP is available }
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CPUX86_HAS_OSXSAVE { XGETBV is available }
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);
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tfpuflags =
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(FPUX86_HAS_AVXUNIT,
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FPUX86_HAS_FMA,
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FPUX86_HAS_FMA4,
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FPUX86_HAS_AVX2,
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FPUX86_HAS_AVX512F,
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FPUX86_HAS_AVX512BW,
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FPUX86_HAS_AVX512CD,
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FPUX86_HAS_AVX512VL,
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FPUX86_HAS_AVX512DQ
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);
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{ Instruction optimisation hints }
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TCPUOptimizeFlags =
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(CPUX86_HINT_FAST_BT_REG_IMM, { BT instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_REG_REG, { BT instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_REG_IMM, { BTC/R/S instructions with register source and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_REG_REG, { BTC/R/S instructions with register source and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BT_MEM_IMM, { BT instructions with memory sources and inmediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BT_MEM_REG, { BT instructions with memory sources and register indices and a register index are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_IMM, { BTC/R/S instructions with memory sources and immediate indices are at least as fast as logical instructions }
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CPUX86_HINT_FAST_BTX_MEM_REG, { BTC/R/S instructions with memory sources and register indices are at least as fast as equivalent logical instructions }
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CPUX86_HINT_FAST_XCHG, { XCHG %reg,%reg executes in 2 cycles or fewer }
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CPUX86_HINT_FAST_PDEP_PEXT, { The BMI2 instructions PDEP and PEXT execute in a single cycle }
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CPUX86_HINT_FAST_3COMP_ADDR, { A 3-component address (base, index and offset) has the same latency as the 2-component version (most notable with LEA instructions) }
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CPUX86_HINT_FAST_SHORT_REP_MOVS, { short rep movs instruction }
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CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1 { BSR/F does not change the destination if ZF is set }
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);
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const
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cpu_capabilities : array[tcputype] of set of tcpuflags = (
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{ cpu_none } [],
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{ cpu_386 } [CPUX86_HAS_BTX],
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{ cpu_486 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX],
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{ cpu_Pentium } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX],
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{ cpu_Pentium2 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV],
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{ cpu_Pentium3 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT],
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{ cpu_Pentium4 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_PentiumM } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2],
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{ cpu_core_i } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT],
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{ cpu_bobcat } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_POPCNT,CPUX86_HAS_LZCNT],
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{ cpu_core_avx } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT],
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{ cpu_jaguar } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_piledriver} [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_excavator } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_core_avx2 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen2 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_skylake_x } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_icelake } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_icelake_client } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_icelake_server } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen3 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen4 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE],
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{ cpu_zen5 } [CPUX86_HAS_BSWAP,CPUX86_HAS_BTX,CPUX86_HAS_CMOV,CPUX86_HAS_SSEUNIT,CPUX86_HAS_SSE2,CPUX86_HAS_SSSE3,CPUX86_HAS_SSE4_1,CPUX86_HAS_POPCNT,CPUX86_HAS_BMI1,CPUX86_HAS_BMI2,CPUX86_HAS_LZCNT,CPUX86_HAS_MOVBE]
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);
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fpu_capabilities : array[tfputype] of set of tfpuflags = (
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{ fpu_none } [],
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{ fpu_x87 } [],
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{ fpu_sse } [],
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{ fpu_sse2 } [],
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{ fpu_sse3 } [],
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{ fpu_ssse3 } [],
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{ fpu_sse41 } [],
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{ fpu_sse42 } [],
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{ fpu_avx } [FPUX86_HAS_AVXUNIT],
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{ fpu_fma } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA],
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{ fpu_avx2 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA,FPUX86_HAS_AVX2],
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{ fpu_avx512 } [FPUX86_HAS_AVXUNIT,FPUX86_HAS_FMA,FPUX86_HAS_AVX2,FPUX86_HAS_AVX512F,FPUX86_HAS_AVX512VL,FPUX86_HAS_AVX512DQ]
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);
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cpu_optimization_hints : array[TCPUType] of set of TCPUOptimizeFlags = (
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{ cpu_none } [],
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{ cpu_386 } [CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_486 } [CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_Pentium } [CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_Pentium2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_Pentium3 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_Pentium4 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM],
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{ cpu_PentiumM } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_core_i } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_bobcat } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_core_avx } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG], { From Sandy Bridge up to Ice Lake, complex LEA instructions are much slower }
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{ cpu_jaguar } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_piledriver} [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_excavator } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_core_avx2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT],
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{ cpu_zen } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_zen2 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_skylake_x } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR],
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{ cpu_icelake } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS],
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{ cpu_icelake_client } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS],
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{ cpu_icelake_server } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS],
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{ cpu_zen3 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_zen4 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1],
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{ cpu_zen5 } [CPUX86_HINT_FAST_BT_REG_IMM,CPUX86_HINT_FAST_BTX_REG_IMM,CPUX86_HINT_FAST_BT_MEM_IMM,CPUX86_HINT_FAST_XCHG,CPUX86_HINT_FAST_PDEP_PEXT,CPUX86_HINT_FAST_3COMP_ADDR,CPUX86_HINT_FAST_SHORT_REP_MOVS,CPUX86_HINT_BSX_DEST_UNCHANGED_ON_ZF_1]
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);
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Implementation
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end.
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