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https://gitlab.com/freepascal.org/fpc/source.git
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202 lines
8.6 KiB
ObjectPascal
202 lines
8.6 KiB
ObjectPascal
{
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Copyright (c) 2014 by the Free Pascal development team
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Generate m68k assembler for in memory related nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n68kmem;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,
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symtype,
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cgbase,cpuinfo,cpubase,
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node,nmem,ncgmem;
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type
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t68kvecnode = class(tcgvecnode)
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procedure update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint); override;
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procedure update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l:aint); override;
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//procedure pass_generate_code;override;
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end;
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implementation
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uses
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systems,globals,
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cutils,verbose,
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symdef,paramgr,
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aasmtai,aasmdata,
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nld,ncon,nadd,
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cgutils,cgobj,
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defutil;
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{*****************************************************************************
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T68KVECNODE
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*****************************************************************************}
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{ this routine must, like any other routine, not change the contents }
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{ of base/index registers of references, as these may be regvars. }
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{ The register allocator can coalesce one LOC_REGISTER being moved }
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{ into another (as their live ranges won't overlap), but not a }
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{ LOC_CREGISTER moved into a LOC_(C)REGISTER most of the time (as }
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{ the live range of the LOC_CREGISTER will most likely overlap the }
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{ the live range of the target LOC_(C)REGISTER) }
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{ The passed register may be a LOC_CREGISTER as well. }
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procedure t68kvecnode.update_reference_reg_mul(maybe_const_reg: tregister; regsize: tdef; l: aint);
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var
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hreg: tregister;
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scaled: boolean;
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regcgsize: tcgsize;
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begin
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scaled:=false;
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regcgsize:=def_cgsize(regsize);
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: called')));
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if l<>1 then
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begin
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: l <> 1')));
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{ if we have a possibility, setup a scalefactor instead of the MUL }
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if not (((CPUM68K_HAS_INDEXSCALE in cpu_capabilities[current_settings.cputype]) and (l in [2,4])) or
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((CPUM68K_HAS_INDEXSCALE8 in cpu_capabilities[current_settings.cputype]) and (l in [2,4,8]))) then
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begin
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: mul')));
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hreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,regcgsize,OS_ADDR,maybe_const_reg,hreg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_ADDR,l,hreg);
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regcgsize:=OS_ADDR;
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maybe_const_reg:=hreg;
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end
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else
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begin
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: scale')));
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scaled:=true;
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end;
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end;
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if (location.reference.base=NR_NO) and not (scaled) and not assigned(location.reference.symbol) then
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begin
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{ prefer an address reg, if we will be a base, for indexes any register works }
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if isintregister(maybe_const_reg) then
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begin
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: copytoa')));
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,regcgsize,OS_ADDR,maybe_const_reg,hreg);
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maybe_const_reg:=hreg;
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end;
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location.reference.base:=maybe_const_reg;
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end
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else
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begin
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if location.reference.index<>NR_NO then
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begin
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{ if we already have an index register, dereference the ref to a new base, to be able to insert an index }
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hreg:=cg.getaddressregister(current_asmdata.CurrAsmList);
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cg.a_loadaddr_ref_reg(current_asmdata.CurrAsmList,location.reference,hreg);
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reference_reset_base(location.reference,hreg,0,location.reference.temppos,location.reference.alignment,location.reference.volatility);
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end;
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if regcgsize in [OS_8,OS_16] then
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begin
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{ index registers are always sign extended on m68k, so we have to zero extend by hand,
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if the index variable is unsigned, and its width is less than the whole register }
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//current_asmdata.CurrAsmList.concat(tai_comment.create(strpnew('updref: index zero extend')));
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hreg:=cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_load_reg_reg(current_asmdata.CurrAsmList,regcgsize,OS_ADDR,maybe_const_reg,hreg);
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maybe_const_reg:=hreg;
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end;
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{ insert new index register }
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location.reference.index:=maybe_const_reg;
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if (scaled) then
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location.reference.scalefactor:=l;
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end;
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{ update alignment }
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if (location.reference.alignment=0) then
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internalerror(2009020704);
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location.reference.alignment:=newalignment(location.reference.alignment,l);
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end;
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{ see remarks for tcgvecnode.update_reference_reg_mul above }
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procedure t68kvecnode.update_reference_reg_packed(maybe_const_reg: tregister; regsize: tdef; l:aint);
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var
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sref: tsubsetreference;
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offsetreg, hreg: tregister;
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alignpower: aint;
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temp : longint;
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begin
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{ only orddefs are bitpacked. Even then we only need special code in }
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{ case the bitpacked *byte size* is not a power of two, otherwise }
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{ everything can be handled using the the regular array code. }
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if ((l mod 8) = 0) and
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(ispowerof2(l div 8,temp) or
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not is_ordinal(resultdef)
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{$ifndef cpu64bitalu}
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or is_64bitint(resultdef)
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{$endif not cpu64bitalu}
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) then
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begin
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update_reference_reg_mul(maybe_const_reg,regsize,l div 8);
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exit;
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end;
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if (l > 8*sizeof(aint)) then
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internalerror(2006080503);
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sref.ref := location.reference;
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hreg := cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SUB,OS_INT,tarraydef(left.resultdef).lowrange,maybe_const_reg,hreg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_IMUL,OS_INT,l,hreg);
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{ keep alignment for index }
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sref.ref.alignment := left.resultdef.alignment;
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if not ispowerof2(packedbitsloadsize(l),temp) then
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internalerror(2006081201);
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alignpower:=temp;
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offsetreg := cg.getintregister(current_asmdata.CurrAsmList,OS_ADDR);
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,OP_SHR,OS_ADDR,3+alignpower,hreg,offsetreg);
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_SHL,OS_ADDR,alignpower,offsetreg);
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if (sref.ref.base = NR_NO) then
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sref.ref.base := offsetreg
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else if (sref.ref.index = NR_NO) then
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sref.ref.index := offsetreg
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else
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begin
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cg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_ADD,OS_ADDR,sref.ref.base,offsetreg);
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sref.ref.base := offsetreg;
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end;
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cg.a_op_const_reg(current_asmdata.CurrAsmList,OP_AND,OS_INT,(1 shl (3+alignpower))-1,hreg);
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sref.bitindexreg := hreg;
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sref.startbit := 0;
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sref.bitlen := resultdef.packedbitsize;
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if (left.location.loc = LOC_REFERENCE) then
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location.loc := LOC_SUBSETREF
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else
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location.loc := LOC_CSUBSETREF;
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location.sref := sref;
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end;
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{procedure t68kvecnode.pass_generate_code;
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begin
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inherited pass_generate_code;
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end;}
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begin
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cvecnode:=t68kvecnode;
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end.
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