florian a502921481 * overleft formatting issue		2025-11-03 21:55:08 +01:00
..
aoptcpu.pas	* cleanup	2025-09-20 23:14:42 +02:00
aoptcpub.pas
aoptcpuc.pas
aoptcpud.pas
cgcpu.pas	* overleft formatting issue	2025-11-03 21:55:08 +01:00
cpuinfo.pas	Make Zicsr and Zifencei explicitly part of subarch name since it is not included in the base ISA 20191213	2025-10-16 21:53:48 +02:00
cpunode.pas	+ RiscV: make use of the fmv.w.x/fmv.d.x instruction to load 0.0	2025-01-11 21:03:54 +01:00
cpupara.pas	* RiscV: push_addr_param unified	2024-12-26 16:49:43 +01:00
cpupi.pas
cputarg.pas
hlcgcpu.pas
nrv32add.pas
nrv32cal.pas
nrv32cnv.pas
nrv32mat.pas	* emit_div/mod_reg_reg_reg takes now three operands	2025-09-17 22:40:28 +02:00
nrv32util.pas	* fixes RiscV32 building	2024-12-25 22:48:40 +01:00
rrv32con.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32dwa.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32nor.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32num.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32rni.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sri.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sta.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32std.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
rrv32sup.inc	+ RiscV: vector registers	2024-12-25 10:34:46 +01:00
symcpu.pas
tripletcpu.pas