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338 lines
12 KiB
ObjectPascal
338 lines
12 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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This unit implements the code generator for the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgcpu;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,parabase,
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cgbase,cgutils,cgobj,
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cg64f32,
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aasmbase,aasmtai,aasmdata,aasmcpu,
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cpubase,cpuinfo,
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node,symconst,SymType,symdef,
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rgcpu,
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cgsparc;
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type
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TCGSparc=class(TCGSparcGen)
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procedure a_load_reg_reg(list : TAsmList; fromsize,tosize : tcgsize; reg1,reg2 : tregister);override;
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procedure a_load_const_reg(list : TAsmList; size : TCGSize; a : tcgint; reg : TRegister);override;
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end;
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TCg64Sparc=class(tcg64f32)
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private
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procedure get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp;checkoverflow : boolean);
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public
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procedure a_load64_reg_ref(list : TAsmList;reg : tregister64;const ref : treference);override;
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procedure a_load64_ref_reg(list : TAsmList;const ref : treference;reg : tregister64);override;
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procedure a_load64_ref_cgpara(list : TAsmList;const r : treference;const paraloc : tcgpara);override;
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procedure a_op64_reg_reg(list:TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst:TRegister64);override;
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procedure a_op64_const_reg(list:TAsmList;op:TOpCG;size : tcgsize;value:int64;regdst:TRegister64);override;
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procedure a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64);override;
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procedure a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);override;
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procedure a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
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procedure a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);override;
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end;
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procedure create_codegen;
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implementation
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uses
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verbose,
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systems;
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procedure TCGSparc.a_load_reg_reg(list:TAsmList;fromsize,tosize:tcgsize;reg1,reg2:tregister);
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var
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instr : taicpu;
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begin
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if (tcgsize2size[fromsize] > tcgsize2size[tosize]) or
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((tcgsize2size[fromsize] = tcgsize2size[tosize]) and
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(fromsize <> tosize)) or
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{ needs to mask out the sign in the top 16 bits }
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((fromsize = OS_S8) and
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(tosize = OS_16)) then
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case tosize of
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OS_8 :
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list.concat(taicpu.op_reg_const_reg(A_AND,reg1,$ff,reg2));
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OS_16 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,16,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRL,reg2,16,reg2));
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end;
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OS_32,
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OS_S32 :
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begin
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instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
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list.Concat(instr);
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{ Notify the register allocator that we have written a move instruction so
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it can try to eliminate it. }
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add_move_instruction(instr);
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end;
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OS_S8 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,24,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,24,reg2));
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end;
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OS_S16 :
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begin
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list.concat(taicpu.op_reg_const_reg(A_SLL,reg1,16,reg2));
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list.concat(taicpu.op_reg_const_reg(A_SRA,reg2,16,reg2));
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end;
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else
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internalerror(2002090901);
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end
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else
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begin
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instr:=taicpu.op_reg_reg(A_MOV,reg1,reg2);
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list.Concat(instr);
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{ Notify the register allocator that we have written a move instruction so
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it can try to eliminate it. }
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add_move_instruction(instr);
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end;
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end;
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procedure TCGSparc.a_load_const_reg(list : TAsmList;size : TCGSize;a : tcgint;reg : TRegister);
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begin
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{ we don't use the set instruction here because it could be evalutated to two
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instructions which would cause problems with the delay slot (FK) }
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if (a=0) then
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list.concat(taicpu.op_reg(A_CLR,reg))
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else if (a>=simm13lo) and (a<=simm13hi) then
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list.concat(taicpu.op_const_reg(A_MOV,a,reg))
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else
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begin
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list.concat(taicpu.op_const_reg(A_SETHI,aint(a) shr 10,reg));
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if (aint(a) and aint($3ff))<>0 then
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list.concat(taicpu.op_reg_const_reg(A_OR,reg,aint(a) and aint($3ff),reg));
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end;
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end;
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{****************************************************************************
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TCG64Sparc
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****************************************************************************}
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procedure tcg64sparc.a_load64_reg_ref(list : TAsmList;reg : tregister64;const ref : treference);
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var
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tmpref: treference;
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begin
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{ Override this function to prevent loading the reference twice }
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tmpref:=ref;
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cg.a_load_reg_ref(list,OS_32,OS_32,reg.reghi,tmpref);
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inc(tmpref.offset,4);
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cg.a_load_reg_ref(list,OS_32,OS_32,reg.reglo,tmpref);
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end;
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procedure tcg64sparc.a_load64_ref_reg(list : TAsmList;const ref : treference;reg : tregister64);
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var
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tmpref: treference;
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begin
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{ Override this function to prevent loading the reference twice }
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tmpref:=ref;
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reghi);
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inc(tmpref.offset,4);
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cg.a_load_ref_reg(list,OS_32,OS_32,tmpref,reg.reglo);
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end;
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procedure tcg64sparc.a_load64_ref_cgpara(list : TAsmList;const r : treference;const paraloc : tcgpara);
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var
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hreg64 : tregister64;
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begin
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{ Override this function to prevent loading the reference twice.
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Use here some extra registers, but those are optimized away by the RA }
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hreg64.reglo:=cg.GetIntRegister(list,OS_32);
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hreg64.reghi:=cg.GetIntRegister(list,OS_32);
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a_load64_ref_reg(list,r,hreg64);
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a_load64_reg_cgpara(list,hreg64,paraloc);
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end;
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procedure TCg64Sparc.get_64bit_ops(op:TOpCG;var op1,op2:TAsmOp;checkoverflow : boolean);
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begin
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case op of
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OP_ADD :
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begin
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op1:=A_ADDCC;
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if checkoverflow then
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op2:=A_ADDXCC
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else
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op2:=A_ADDX;
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end;
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OP_SUB :
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begin
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op1:=A_SUBCC;
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if checkoverflow then
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op2:=A_SUBXCC
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else
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op2:=A_SUBX;
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end;
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OP_XOR :
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begin
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op1:=A_XOR;
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op2:=A_XOR;
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end;
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OP_OR :
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begin
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op1:=A_OR;
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op2:=A_OR;
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end;
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OP_AND :
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begin
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op1:=A_AND;
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op2:=A_AND;
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end;
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else
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internalerror(2002032409);
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end;
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end;
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procedure TCg64Sparc.a_op64_reg_reg(list:TAsmList;op:TOpCG;size : tcgsize;regsrc,regdst:TRegister64);
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begin
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case op of
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OP_NEG :
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begin
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{ Use the simple code: y=0-z }
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list.concat(taicpu.op_reg_reg_reg(A_SUBcc,NR_G0,regsrc.reglo,regdst.reglo));
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list.concat(taicpu.op_reg_reg_reg(A_SUBX,NR_G0,regsrc.reghi,regdst.reghi));
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end;
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OP_NOT :
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begin
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list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reglo,NR_G0,regdst.reglo));
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list.concat(taicpu.op_reg_reg_reg(A_XNOR,regsrc.reghi,NR_G0,regdst.reghi));
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end;
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else
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a_op64_reg_reg_reg(list,op,size,regsrc,regdst,regdst);
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end;
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end;
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procedure TCg64Sparc.a_op64_const_reg(list:TAsmList;op:TOpCG;size : tcgsize;value:int64;regdst:TRegister64);
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begin
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a_op64_const_reg_reg(list,op,size,value,regdst,regdst);
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end;
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procedure tcg64sparc.a_op64_const_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;value : int64; regsrc,regdst : tregister64);
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var
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l : tlocation;
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begin
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a_op64_const_reg_reg_checkoverflow(list,op,size,value,regsrc,regdst,false,l);
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end;
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procedure tcg64sparc.a_op64_reg_reg_reg(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64);
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var
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l : tlocation;
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begin
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a_op64_reg_reg_reg_checkoverflow(list,op,size,regsrc1,regsrc2,regdst,false,l);
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end;
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procedure tcg64sparc.a_op64_const_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;value : int64;regsrc,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
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var
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op1,op2:TAsmOp;
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fl:TSparcFlags;
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begin
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case op of
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OP_NEG,
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OP_NOT :
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internalerror(2003060102);
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OP_AND,OP_OR,OP_XOR:
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begin
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cg.a_op_const_reg_reg(list,op,OS_INT,tcgint(lo(value)),regsrc.reglo,regdst.reglo);
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cg.a_op_const_reg_reg(list,op,OS_INT,tcgint(hi(value)),regsrc.reghi,regdst.reghi);
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end;
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else
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get_64bit_ops(op,op1,op2,setflags);
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tcgsparc(cg).handle_reg_const_reg(list,op1,regsrc.reglo,tcgint(lo(value)),regdst.reglo);
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tcgsparc(cg).handle_reg_const_reg(list,op2,regsrc.reghi,tcgint(hi(value)),regdst.reghi);
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end;
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if setflags then
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begin
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ovloc.loc:=LOC_FLAGS;
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if size=OS_S64 then
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fl:=F_VS
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else if size=OS_64 then
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fl:=F_B
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else
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internalerror(2024040301);
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ovloc.resflags.Init(NR_ICC,fl);
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end
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else
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ovloc.loc:=LOC_INVALID;
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end;
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procedure tcg64sparc.a_op64_reg_reg_reg_checkoverflow(list: TAsmList;op:TOpCG;size : tcgsize;regsrc1,regsrc2,regdst : tregister64;setflags : boolean;var ovloc : tlocation);
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var
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op1,op2:TAsmOp;
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fl:TSparcFlags;
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begin
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case op of
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OP_NEG,
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OP_NOT :
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internalerror(2003060103);
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else
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;
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end;
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get_64bit_ops(op,op1,op2,setflags);
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list.concat(taicpu.op_reg_reg_reg(op1,regsrc2.reglo,regsrc1.reglo,regdst.reglo));
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list.concat(taicpu.op_reg_reg_reg(op2,regsrc2.reghi,regsrc1.reghi,regdst.reghi));
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if setflags then
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begin
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ovloc.loc:=LOC_FLAGS;
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if size=OS_S64 then
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fl:=F_VS
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else if size=OS_64 then
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fl:=F_B
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else
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internalerror(2024040301);
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ovloc.resflags.Init(NR_ICC,fl);
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end
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else
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ovloc.loc:=LOC_INVALID;
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end;
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procedure create_codegen;
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begin
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cg:=TCgSparc.Create;
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if target_info.system=system_sparc_linux then
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TCgSparc(cg).use_unlimited_pic_mode:=true
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else
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TCgSparc(cg).use_unlimited_pic_mode:=false;
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cg64:=TCg64Sparc.Create;
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end;
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end.
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