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ce598c15ec
overflow checks
o in particular ensure that cpu-specific overrides don't perform overflow
checks when nf_internal is set
git-svn-id: trunk@42573 -
529 lines
18 KiB
ObjectPascal
529 lines
18 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl
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Code generation for add nodes on the SPARC
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit ncpuadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,ncgadd,cpubase;
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type
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tsparcaddnode = class(tcgaddnode)
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private
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function GetResFlags(unsigned,use64bit:Boolean):TResFlags;
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function GetFPUResFlags:TResFlags;
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protected
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procedure second_addfloat;override;
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procedure second_cmpfloat;override;
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procedure second_cmpboolean;override;
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procedure second_cmpsmallset;override;
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procedure second_cmp64bit;override;
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procedure second_add64bit;override;
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procedure second_cmpordinal;override;
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procedure second_addordinal;override;
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public
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function pass_1: tnode; override;
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function use_generic_mul32to64: boolean; override;
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function use_generic_mul64bit : boolean; override;
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end;
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implementation
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uses
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systems,
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globals,globtype,
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cutils,verbose,
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paramgr,procinfo,
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aasmtai,aasmdata,aasmcpu,defutil,
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cgbase,cgsparc,cgcpu,cgutils,
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cpuinfo,cpupara,
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ncon,nset,nadd,
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hlcgobj,ncgutil,cgobj;
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{*****************************************************************************
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TSparcAddNode
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*****************************************************************************}
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function TSparcAddNode.GetResFlags(unsigned,use64bit:Boolean):TResFlags;
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var
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flagreg : TRegister;
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begin
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{$ifdef SPARC64}
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if use64bit then
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flagreg:=NR_XCC
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else
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{$endif SPARC64}
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flagreg:=NR_ICC;
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case NodeType of
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equaln:
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GetResFlags.Init(flagreg,F_E);
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unequaln:
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GetResFlags.Init(flagreg,F_NE);
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else
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if not(unsigned) then
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begin
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if nf_swapped in flags then
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case NodeType of
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ltn:
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GetResFlags.Init(flagreg,F_G);
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lten:
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GetResFlags.Init(flagreg,F_GE);
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gtn:
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GetResFlags.Init(flagreg,F_L);
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gten:
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GetResFlags.Init(flagreg,F_LE);
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else
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internalerror(2014082010);
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end
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else
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case NodeType of
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ltn:
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GetResFlags.Init(flagreg,F_L);
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lten:
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GetResFlags.Init(flagreg,F_LE);
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gtn:
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GetResFlags.Init(flagreg,F_G);
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gten:
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GetResFlags.Init(flagreg,F_GE);
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else
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internalerror(2014082011);
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end;
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end
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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GetResFlags.Init(flagreg,F_A);
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lten:
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GetResFlags.Init(flagreg,F_AE);
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gtn:
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GetResFlags.Init(flagreg,F_B);
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gten:
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GetResFlags.Init(flagreg,F_BE);
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else
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internalerror(2014082012);
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end
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else
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case NodeType of
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ltn:
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GetResFlags.Init(flagreg,F_B);
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lten:
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GetResFlags.Init(flagreg,F_BE);
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gtn:
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GetResFlags.Init(flagreg,F_A);
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gten:
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GetResFlags.Init(flagreg,F_AE);
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else
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internalerror(2014082013);
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end;
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end;
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end;
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end;
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function TSparcAddNode.GetFPUResFlags:TResFlags;
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begin
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case NodeType of
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equaln:
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result.Init(NR_FCC0,F_FE);
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unequaln:
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result.Init(NR_FCC0,F_FNE);
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else
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begin
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if nf_swapped in Flags then
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case NodeType of
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ltn:
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result.Init(NR_FCC0,F_FG);
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lten:
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result.Init(NR_FCC0,F_FGE);
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gtn:
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result.Init(NR_FCC0,F_FL);
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gten:
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result.Init(NR_FCC0,F_FLE);
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else
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internalerror(2014082014);
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end
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else
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case NodeType of
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ltn:
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result.Init(NR_FCC0,F_FL);
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lten:
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result.Init(NR_FCC0,F_FLE);
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gtn:
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result.Init(NR_FCC0,F_FG);
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gten:
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result.Init(NR_FCC0,F_FGE);
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else
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internalerror(2014082015);
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end;
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end;
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end;
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end;
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procedure tsparcaddnode.second_addfloat;
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var
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op : TAsmOp;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,(left.location.loc<>LOC_CFPUREGISTER));
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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if left.location.loc<>LOC_CFPUREGISTER then
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location.register:=left.location.register
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else
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location.register:=right.location.register;
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case nodetype of
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addn :
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begin
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if location.size=OS_F64 then
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op:=A_FADDd
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else
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op:=A_FADDs;
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end;
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muln :
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begin
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if location.size=OS_F64 then
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op:=A_FMULd
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else
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op:=A_FMULs;
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end;
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subn :
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begin
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if location.size=OS_F64 then
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op:=A_FSUBd
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else
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op:=A_FSUBs;
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end;
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slashn :
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begin
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if location.size=OS_F64 then
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op:=A_FDIVd
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else
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op:=A_FDIVs;
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end;
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else
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internalerror(200306014);
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(op,
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left.location.register,right.location.register,location.register));
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end;
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procedure tsparcaddnode.second_cmpfloat;
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var
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op : tasmop;
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begin
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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{ force fpureg as location, left right doesn't matter
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as both will be in a fpureg }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getfpuresflags;
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if left.location.size=OS_F64 then
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op:=A_FCMPd
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else
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op:=A_FCMPs;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg(op,
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left.location.register,right.location.register));
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{$ifdef SPARC32}
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{ Delay slot (can only contain integer operation) }
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if current_settings.cputype in [cpu_SPARC_V7,cpu_SPARC_V8] then
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current_asmdata.CurrAsmList.concat(taicpu.op_none(A_NOP));
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{$endif SPARC32}
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end;
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procedure tsparcaddnode.second_cmpboolean;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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if right.location.loc = LOC_CONSTANT then
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tcgsparcgen(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_SUBcc,left.location.register,right.location.value,NR_G0)
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(true,is_64bit(right.resultdef));
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end;
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procedure tsparcaddnode.second_cmpsmallset;
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var
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tmpreg : tregister;
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begin
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pass_left_right;
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location_reset(location,LOC_FLAGS,OS_NO);
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force_reg_left_right(false,false);
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case nodetype of
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equaln,
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unequaln:
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begin
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location.resflags:=getresflags(true,is_64bit(right.resultdef));
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end;
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lten,
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gten:
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begin
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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tmpreg:=cg.getintregister(current_asmdata.CurrAsmList,left.location.size);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_AND,left.location.register,right.location.register,tmpreg));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,tmpreg,right.location.register,NR_G0));
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location.resflags.Init(NR_ICC,F_E);
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end;
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else
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internalerror(2012042701);
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end;
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end;
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procedure tsparcaddnode.second_add64bit;
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begin
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{$ifdef SPARC64}
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second_addordinal;
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{$else SPARC64}
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inherited second_add64bit;
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{$endif SPARC64}
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end;
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procedure tsparcaddnode.second_cmp64bit;
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{$ifdef SPARC64}
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begin
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second_cmpordinal;
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end;
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{$else SPARC64}
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var
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unsigned : boolean;
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hreg1,hreg2: tregister;
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procedure emit_compare(list:tasmlist; ls,rs:tnode);
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var
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lreg: tregister64;
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begin
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if (ls.location.loc=LOC_CONSTANT) then
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begin
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lreg.reghi:=NR_G0;
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lreg.reglo:=NR_G0;
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if lo(ls.location.value64)<>0 then
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begin
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lreg.reglo:=cg.GetIntRegister(list,OS_INT);
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cg.a_load_const_reg(list,OS_INT,lo(ls.location.value64),lreg.reglo);
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end;
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if hi(ls.location.value64)<>0 then
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begin
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lreg.reghi:=cg.GetIntRegister(list,OS_INT);
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cg.a_load_const_reg(list,OS_INT,hi(ls.location.value64),lreg.reghi);
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end;
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end
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else
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lreg:=ls.location.register64;
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if (rs.location.loc=LOC_CONSTANT) then
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begin
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tcgsparcgen(cg).handle_reg_const_reg(list,A_SUBcc,lreg.reglo,lo(rs.location.value64),NR_G0);
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tcgsparcgen(cg).handle_reg_const_reg(list,A_SUBXcc,lreg.reghi,hi(rs.location.value64),NR_G0);
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end
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else
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SUBcc,lreg.reglo,rs.location.register64.reglo,NR_G0));
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list.concat(taicpu.op_reg_reg_reg(A_SUBXcc,lreg.reghi,rs.location.register64.reghi,NR_G0));
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end;
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end;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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location_reset(location,LOC_FLAGS,OS_NO);
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if (nodetype in [equaln,unequaln]) then
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begin
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location.resflags:=getresflags(unsigned,false);
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if (right.location.loc=LOC_CONSTANT) then
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begin
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if hi(right.location.value64)<>0 then
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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tcgsparcgen(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_XOR,left.location.register64.reghi,hi(right.location.value64),hreg1);
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end
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else
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hreg1:=left.location.register64.reghi;
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if lo(right.location.value64)<>0 then
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begin
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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tcgsparcgen(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_XOR,left.location.register64.reglo,lo(right.location.value64),hreg2);
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end
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else
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hreg2:=left.location.register64.reglo;
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end
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else
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begin
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hreg1:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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hreg2:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_XOR,left.location.register64.reghi,right.location.register64.reghi,hreg1));
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_XOR,left.location.register64.reglo,right.location.register64.reglo,hreg2));
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end;
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_ORcc,hreg1,hreg2,NR_G0));
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end
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else
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begin
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{ undo possible swapped state }
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if (nf_swapped in flags) then
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swapleftright;
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{ Subtracting sides sets N,V and C flags correctly, but not Z flag
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(which ends up depending only on upper dword). So don't use conditions
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that test Z flag:
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unsigned signed
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a < b => F_B F_L
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a >= b => F_AE F_GE
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a <= b => swap, F_AE F_GE
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a > b => swap, F_B F_L }
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if (nodetype in [ltn,gten]) then
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begin
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emit_compare(current_asmdata.CurrAsmList,left,right);
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location.resflags:=getresflags(unsigned,false);
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end
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else if (nodetype in [lten,gtn]) then
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begin
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emit_compare(current_asmdata.CurrAsmList,right,left);
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toggleflag(nf_swapped);
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location.resflags:=getresflags(unsigned,false);
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toggleflag(nf_swapped);
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end
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else
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InternalError(2014011001);
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end;
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end;
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{$endif SPARC64}
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procedure tsparcaddnode.second_cmpordinal;
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var
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unsigned : boolean;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if right.location.loc = LOC_CONSTANT then
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tcgsparcgen(cg).handle_reg_const_reg(current_asmdata.CurrAsmList,A_SUBcc,left.location.register,right.location.value,NR_G0)
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else
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current_asmdata.CurrAsmList.concat(taicpu.op_reg_reg_reg(A_SUBcc,left.location.register,right.location.register,NR_G0));
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location_reset(location,LOC_FLAGS,OS_NO);
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location.resflags:=getresflags(unsigned,is_64bit(right.resultdef));
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end;
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const
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multops: array[boolean] of TAsmOp = (A_SMUL, A_UMUL);
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procedure tsparcaddnode.second_addordinal;
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var
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unsigned: boolean;
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begin
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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if (nodetype=muln) and is_64bit(resultdef) then
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begin
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pass_left_right;
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force_reg_left_right(true,false);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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{$ifdef SPARC64}
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,location.size);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(A_MULX,left.location.register,right.location.register,location.register));
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{$else SPARC64}
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location.register64.reglo:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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location.register64.reghi:=cg.getintregister(current_asmdata.CurrAsmList,OS_INT);
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg_reg(multops[unsigned],left.location.register,right.location.register,location.register64.reglo));
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current_asmdata.CurrAsmList.Concat(taicpu.op_reg_reg(A_MOV,NR_Y,location.register64.reghi));
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{$endif SPARC64}
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end
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else
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inherited second_addordinal;
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end;
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function tsparcaddnode.use_generic_mul32to64: boolean;
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begin
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result:=false;
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end;
|
|
|
|
|
|
function tsparcaddnode.use_generic_mul64bit: boolean;
|
|
begin
|
|
{$ifdef SPARC64}
|
|
result:=needoverflowcheck;
|
|
{$else SPARC64}
|
|
result:=inherited;
|
|
{$endif SPARC64}
|
|
end;
|
|
|
|
|
|
function tsparcaddnode.pass_1: tnode;
|
|
begin
|
|
result:=inherited pass_1;
|
|
if not assigned(result) then
|
|
begin
|
|
if is_64bitint(left.resultdef) and
|
|
(nodetype in [equaln,unequaln,ltn,gtn,lten,gten]) then
|
|
expectloc:=LOC_FLAGS;
|
|
end;
|
|
end;
|
|
|
|
begin
|
|
caddnode:=tsparcaddnode;
|
|
end.
|