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110 lines
3.5 KiB
ObjectPascal
110 lines
3.5 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate x86-64 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nx64mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,nx86mat;
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type
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tx8664shlshrnode = class(tx86shlshrnode)
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procedure pass_generate_code;override;
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end;
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tx8664unaryminusnode = class(tx86unaryminusnode)
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end;
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tx8664notnode = class(tx86notnode)
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end;
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implementation
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uses
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globtype,constexp,
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cutils,
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aasmdata,defutil,
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pass_2,
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ncon,
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cgbase,cgutils,cgobj,hlcgobj;
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{*****************************************************************************
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TX8664SHLRSHRNODE
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*****************************************************************************}
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procedure tx8664shlshrnode.pass_generate_code;
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var
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op : topcg;
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opsize : tcgsize;
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mask : aint;
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begin
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secondpass(left);
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secondpass(right);
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{ determine operator }
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if nodetype=shln then
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op:=OP_SHL
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else
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op:=OP_SHR;
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opsize:=def_cgsize(resultdef);
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mask:=max(resultdef.size,4)*8-1;
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{ load left operators in a register }
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if not(left.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
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{ location_force_reg can be also used to change the size of a register }
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(left.location.size<>opsize) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,cgsize_orddef(opsize),true);
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location_reset(location,LOC_REGISTER,opsize);
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location.register:=cg.getintregister(current_asmdata.CurrAsmList,opsize);
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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cg.a_op_const_reg_reg(current_asmdata.CurrAsmList,op,location.size,
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tordconstnode(right).value.uvalue and mask,left.location.register,location.register)
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else
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begin
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{ load right operators in a register - this
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is done since most target cpu which will use this
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node do not support a shift count in a mem. location (cec)
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}
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if not(right.location.loc in [LOC_CREGISTER,LOC_REGISTER]) or
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{ location_force_reg can be also used to change the size of a register }
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(right.location.size<>opsize) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,cgsize_orddef(opsize),true);
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cg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,op,opsize,right.location.register,left.location.register,location.register);
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end;
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end;
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begin
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cunaryminusnode:=tx8664unaryminusnode;
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cmoddivnode:=tx86moddivnode;
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cshlshrnode:=tx8664shlshrnode;
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cnotnode:=tx8664notnode;
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end.
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