mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-05 15:47:54 +02:00
a7c0fa0def
+ Added postfix parsing in tattreader.GetToken
- Removed all postfixed versions of OpCodes from the instruction list
+ Added all missing OpCodes from Xtensa ISA
* Changed branch OpCode to A_B, similar to ARM
+ Added missing branch condition flags BCI and BSI
* Updated existing compiler code that referred to the old postfixed instructions
+ Added prefix and postfix handling in TxtensaInstrWriter.WriteInstruction
* Updated TCPUAddNode.second_addfloat to specify .S postfix
* Updated tcpuunaryminusnode.second_float to specify .S postfix
+ Implemented prefix and postfix identification in txtensaattreader.is_asmopcode
* Adapted branch condition extraction to respect postfixes
* Changed itcpugas to call findreg_by_name_table from raatt.pas (same as issue #0037121, difficult to test these changes without including a fix for the register name search problem)
git-svn-id: trunk@45672 -
60 lines
1.6 KiB
ObjectPascal
60 lines
1.6 KiB
ObjectPascal
{
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Copyright (c) 1998-2003 by Carl Eric Codere and Peter Vreman
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Handles the common Xtensa assembler reader routines
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit raxtensa;
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{$i fpcdefs.inc}
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interface
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uses
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cpubase,
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aasmtai,aasmdata,
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rautils;
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type
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TXtensaOperand=class(TOperand)
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end;
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{ TXtensaInstruction }
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TXtensaInstruction=class(TInstruction)
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oppostfix : toppostfix;
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opIsPrefixed : boolean;
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function ConcatInstruction(p:TAsmList) : tai;override;
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end;
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implementation
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uses
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aasmcpu;
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{ TXtensaInstruction }
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function TXtensaInstruction.ConcatInstruction(p:TAsmList) : tai;
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begin
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result:=inherited ConcatInstruction(p);
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(result as taicpu).oppostfix:=oppostfix;
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(result as taicpu).opIsPrefixed:=opIsPrefixed;
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end;
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end.
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