mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-05 05:58:02 +02:00
a7c0fa0def
+ Added postfix parsing in tattreader.GetToken
- Removed all postfixed versions of OpCodes from the instruction list
+ Added all missing OpCodes from Xtensa ISA
* Changed branch OpCode to A_B, similar to ARM
+ Added missing branch condition flags BCI and BSI
* Updated existing compiler code that referred to the old postfixed instructions
+ Added prefix and postfix handling in TxtensaInstrWriter.WriteInstruction
* Updated TCPUAddNode.second_addfloat to specify .S postfix
* Updated tcpuunaryminusnode.second_float to specify .S postfix
+ Implemented prefix and postfix identification in txtensaattreader.is_asmopcode
* Adapted branch condition extraction to respect postfixes
* Changed itcpugas to call findreg_by_name_table from raatt.pas (same as issue #0037121, difficult to test these changes without including a fix for the register name search problem)
git-svn-id: trunk@45672 -
193 lines
1.5 KiB
SQL
193 lines
1.5 KiB
SQL
(
|
|
'',
|
|
'abs',
|
|
'add',
|
|
'addi',
|
|
'addmi',
|
|
'addx2',
|
|
'addx4',
|
|
'addx8',
|
|
'all4',
|
|
'all8',
|
|
'and',
|
|
'andb',
|
|
'andbc',
|
|
'any4',
|
|
'any8',
|
|
'b',
|
|
'break',
|
|
'call0',
|
|
'call4',
|
|
'call8',
|
|
'call12',
|
|
'callx0',
|
|
'callx4',
|
|
'callx8',
|
|
'callx12',
|
|
'ceil',
|
|
'clamps',
|
|
'dhi',
|
|
'dhu',
|
|
'dhwb',
|
|
'dhwbi',
|
|
'dii',
|
|
'diu',
|
|
'diwb',
|
|
'diwbi',
|
|
'dpfl',
|
|
'dpfr',
|
|
'dpfro',
|
|
'dpw',
|
|
'dpwo',
|
|
'dsync',
|
|
'entry',
|
|
'esync',
|
|
'excw',
|
|
'extui',
|
|
'extw',
|
|
'float',
|
|
'floor',
|
|
'idtlb',
|
|
'ihi',
|
|
'ihu',
|
|
'iii',
|
|
'iitlb',
|
|
'iiu',
|
|
'ill',
|
|
'ipf',
|
|
'ipfl',
|
|
'isync',
|
|
'j',
|
|
'jx',
|
|
'l8ui',
|
|
'l16si',
|
|
'l16ui',
|
|
'l32ai',
|
|
'l32e',
|
|
'l32i',
|
|
'l32r',
|
|
'ldct',
|
|
'lddec',
|
|
'ldinc',
|
|
'lict',
|
|
'licw',
|
|
'loop',
|
|
'loopgtz',
|
|
'loopnez',
|
|
'lsi',
|
|
'lsiu',
|
|
'lsx',
|
|
'lsxu',
|
|
'madd',
|
|
'max',
|
|
'maxu',
|
|
'memw',
|
|
'min',
|
|
'minu',
|
|
'mov',
|
|
'moveqz',
|
|
'movf',
|
|
'movgez',
|
|
'movi',
|
|
'movltz',
|
|
'movnez',
|
|
'movsp',
|
|
'movt',
|
|
'msub',
|
|
'mul',
|
|
'mul16',
|
|
'mula',
|
|
'mull',
|
|
'muls',
|
|
'mulsh',
|
|
'muluh',
|
|
'neg',
|
|
'nop',
|
|
'nsa',
|
|
'nsau',
|
|
'oeq',
|
|
'ole',
|
|
'olt',
|
|
'or',
|
|
'orb',
|
|
'orbc',
|
|
'pdtlb',
|
|
'pitlb',
|
|
'quos',
|
|
'quou',
|
|
'rdtlb0',
|
|
'rdtlb1',
|
|
'rems',
|
|
'remu',
|
|
'ret',
|
|
'retw',
|
|
'rfdd',
|
|
'rfde',
|
|
'rfe',
|
|
'rfi',
|
|
'rfme',
|
|
'rfr',
|
|
'rfue',
|
|
'rfwo',
|
|
'rfwu',
|
|
'ritlb0',
|
|
'ritlb1',
|
|
'rotw',
|
|
'round',
|
|
'rsil',
|
|
'rsr',
|
|
'rur',
|
|
's8i',
|
|
's16i',
|
|
's32c1i',
|
|
's32e',
|
|
's32i',
|
|
's32ri',
|
|
'sdct',
|
|
'sext',
|
|
'sict',
|
|
'sicw',
|
|
'simcall',
|
|
'sll',
|
|
'slli',
|
|
'sra',
|
|
'srai',
|
|
'src',
|
|
'srl',
|
|
'srli',
|
|
'ssa8b',
|
|
'ssa8l',
|
|
'ssai',
|
|
'ssi',
|
|
'ssiu',
|
|
'ssl',
|
|
'ssr',
|
|
'ssx',
|
|
'ssxu',
|
|
'sub',
|
|
'subx2',
|
|
'subx4',
|
|
'subx8',
|
|
'syscall',
|
|
'trunc',
|
|
'ueq',
|
|
'ufloat',
|
|
'ule',
|
|
'ult',
|
|
'umul',
|
|
'un',
|
|
'utrunc',
|
|
'waiti',
|
|
'wdtlb',
|
|
'wer',
|
|
'wfr',
|
|
'witlb',
|
|
'wsr',
|
|
'wur',
|
|
'xor',
|
|
'xorb',
|
|
'xsr'
|
|
);
|
|
|
|
|