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https://gitlab.com/freepascal.org/fpc/source.git
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1634 lines
73 KiB
ObjectPascal
1634 lines
73 KiB
ObjectPascal
{$IFNDEF FPC_DOTTEDUNITS}
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unit mk22f51212;
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{$ENDIF FPC_DOTTEDUNITS}
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interface
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{$PACKRECORDS 2}
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{$GOTO ON}
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{$MODESWITCH ADVANCEDRECORDS}
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// ** ###################################################################
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// ** Compilers: ARM Compiler
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// ** Freescale C/C++ for Embedded ARM
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// ** GNU C Compiler
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// ** GNU C Compiler - CodeSourcery Sourcery G++
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// ** IAR ANSI C/C++ Compiler for ARM
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// **
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// ** Reference manual: K22P121M120SF7RM, Rev.0.61, Jan 10, 2014
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// ** Version: rev. 2.3, 2014-01-13
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// **
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// ** Abstract:
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// ** CMSIS Peripheral Access Layer for MK22F51212
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// **
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// ** Copyright: 1997 - 2014 Freescale, Inc. All Rights Reserved.
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// **
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// ** http: www.freescale.com
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// ** mail: support@freescale.com
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// **
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// ** Revisions:
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// ** - rev. 1.0 (2013-07-23)
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// ** Initial version.
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// ** - rev. 1.1 (2013-09-17)
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// ** RM rev. 0.4 update.
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// ** - rev. 2.0 (2013-10-29)
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// ** Register accessor macros added to the memory map.
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// ** Symbols for Processor Expert memory map compatibility added to the memory map.
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// ** Startup file for gcc has been updated according to CMSIS 3.2.
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// ** System initialization updated.
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// ** - rev. 2.1 (2013-10-29)
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// ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
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// ** - rev. 2.2 (2013-12-20)
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// ** Update according to reference manual rev. 0.6,
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// ** - rev. 2.3 (2014-01-13)
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// ** Update according to reference manual rev. 0.61,
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// **
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// ** ###################################################################
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// !
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// * @file MK22F51212.h
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// * @version 2.3
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// * @date 2014-01-13
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// CMSIS Peripheral Access Layer for MK22F51212
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// *
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// * CMSIS Peripheral Access Layer for MK22F51212
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// ----------------------------------------------------------------------------
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// -- MCU activation
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// ----------------------------------------------------------------------------
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// Prevention from multiple including the same memory map
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// Check if another memory map has not been also included
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// * Memory map major version (memory maps with equal major version number are
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// * compatible)
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// * Memory map minor version
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// Macro to calculate address of an aliased word in the peripheral
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// * bitband area for a peripheral register and bit (bit band region 0x40000000 to
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// * 0x400FFFFF).
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// * @param Reg Register to access.
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// * @param Bit Bit number to access.
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// * @return Address of the aliased word in the peripheral bitband area.
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// Macro to access a single bit of a peripheral register (bit band region
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// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
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// * be used for peripherals with 32bit access allowed.
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// * @param Reg Register to access.
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// * @param Bit Bit number to access.
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// * @return Value of the targeted bit in the bit band region.
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// Macro to access a single bit of a peripheral register (bit band region
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// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
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// * be used for peripherals with 16bit access allowed.
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// * @param Reg Register to access.
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// * @param Bit Bit number to access.
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// * @return Value of the targeted bit in the bit band region.
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// Macro to access a single bit of a peripheral register (bit band region
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// * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
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// * be used for peripherals with 8bit access allowed.
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// * @param Reg Register to access.
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// * @param Bit Bit number to access.
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// * @return Value of the targeted bit in the bit band region.
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// ----------------------------------------------------------------------------
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// -- Interrupt vector numbers
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// ----------------------------------------------------------------------------
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// !
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// * Interrupt Number Definitions
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type
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TIRQn_Enum = (
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NonMaskableInt_IRQn = -14, // *< Non Maskable Interrupt
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HardFault_IRQn = -13, // *< Cortex-M4 SV Hard Fault Interrupt
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MemoryManagement_IRQn = -12, // *< Cortex-M4 Memory Management Interrupt
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BusFault_IRQn = -11, // *< Cortex-M4 Bus Fault Interrupt
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UsageFault_IRQn = -10, // *< Cortex-M4 Usage Fault Interrupt
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SVCall_IRQn = -5, // *< Cortex-M4 SV Call Interrupt
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DebugMonitor_IRQn = -4, // *< Cortex-M4 Debug Monitor Interrupt
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PendSV_IRQn = -2, // *< Cortex-M4 Pend SV Interrupt
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SysTick_IRQn = -1, // *< Cortex-M4 System Tick Interrupt
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DMA0_IRQn = 0, // *< DMA Channel 0 Transfer Complete
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DMA1_IRQn = 1, // *< DMA Channel 1 Transfer Complete
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DMA2_IRQn = 2, // *< DMA Channel 2 Transfer Complete
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DMA3_IRQn = 3, // *< DMA Channel 3 Transfer Complete
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DMA4_IRQn = 4, // *< DMA Channel 4 Transfer Complete
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DMA5_IRQn = 5, // *< DMA Channel 5 Transfer Complete
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DMA6_IRQn = 6, // *< DMA Channel 6 Transfer Complete
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DMA7_IRQn = 7, // *< DMA Channel 7 Transfer Complete
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DMA8_IRQn = 8, // *< DMA Channel 8 Transfer Complete
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DMA9_IRQn = 9, // *< DMA Channel 9 Transfer Complete
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DMA10_IRQn = 10, // *< DMA Channel 10 Transfer Complete
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DMA11_IRQn = 11, // *< DMA Channel 11 Transfer Complete
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DMA12_IRQn = 12, // *< DMA Channel 12 Transfer Complete
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DMA13_IRQn = 13, // *< DMA Channel 13 Transfer Complete
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DMA14_IRQn = 14, // *< DMA Channel 14 Transfer Complete
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DMA15_IRQn = 15, // *< DMA Channel 15 Transfer Complete
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DMA_Error_IRQn = 16, // *< DMA Error Interrupt
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MCM_IRQn = 17, // *< Normal Interrupt
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FTF_IRQn = 18, // *< FTFA Command complete interrupt
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Read_Collision_IRQn = 19, // *< Read Collision Interrupt
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LVD_LVW_IRQn = 20, // *< Low Voltage Detect, Low Voltage Warning
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LLW_IRQn = 21, // *< Low Leakage Wakeup
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Watchdog_IRQn = 22, // *< WDOG Interrupt
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RNG_IRQn = 23, // *< RNG Interrupt
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I2C0_IRQn = 24, // *< I2C0 interrupt
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I2C1_IRQn = 25, // *< I2C1 interrupt
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SPI0_IRQn = 26, // *< SPI0 Interrupt
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SPI1_IRQn = 27, // *< SPI1 Interrupt
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I2S0_Tx_IRQn = 28, // *< I2S0 transmit interrupt
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I2S0_Rx_IRQn = 29, // *< I2S0 receive interrupt
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LPUART0_IRQn = 30, // *< LPUART0 status/error interrupt
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UART0_RX_TX_IRQn = 31, // *< UART0 Receive/Transmit interrupt
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UART0_ERR_IRQn = 32, // *< UART0 Error interrupt
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UART1_RX_TX_IRQn = 33, // *< UART1 Receive/Transmit interrupt
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UART1_ERR_IRQn = 34, // *< UART1 Error interrupt
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UART2_RX_TX_IRQn = 35, // *< UART2 Receive/Transmit interrupt
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UART2_ERR_IRQn = 36, // *< UART2 Error interrupt
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RESERVED53_IRQn = 37, // *< Reserved interrupt 53
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RESERVED54_IRQn = 38, // *< Reserved interrupt 54
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ADC0_IRQn = 39, // *< ADC0 interrupt
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CMP0_IRQn = 40, // *< CMP0 interrupt
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CMP1_IRQn = 41, // *< CMP1 interrupt
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FTM0_IRQn = 42, // *< FTM0 fault, overflow and channels interrupt
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FTM1_IRQn = 43, // *< FTM1 fault, overflow and channels interrupt
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FTM2_IRQn = 44, // *< FTM2 fault, overflow and channels interrupt
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RESERVED61_IRQn = 45, // *< Reserved interrupt 61
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RTC_IRQn = 46, // *< RTC interrupt
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RTC_Seconds_IRQn = 47, // *< RTC seconds interrupt
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PIT0_IRQn = 48, // *< PIT timer channel 0 interrupt
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PIT1_IRQn = 49, // *< PIT timer channel 1 interrupt
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PIT2_IRQn = 50, // *< PIT timer channel 2 interrupt
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PIT3_IRQn = 51, // *< PIT timer channel 3 interrupt
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PDB0_IRQn = 52, // *< PDB0 Interrupt
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USB0_IRQn = 53, // *< USB0 interrupt
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RESERVED70_IRQn = 54, // *< Reserved interrupt 70
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RESERVED71_IRQn = 55, // *< Reserved interrupt 71
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DAC0_IRQn = 56, // *< DAC0 interrupt
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MCG_IRQn = 57, // *< MCG Interrupt
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LPTimer_IRQn = 58, // *< LPTimer interrupt
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PORTA_IRQn = 59, // *< Port A interrupt
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PORTB_IRQn = 60, // *< Port B interrupt
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PORTC_IRQn = 61, // *< Port C interrupt
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PORTD_IRQn = 62, // *< Port D interrupt
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PORTE_IRQn = 63, // *< Port E interrupt
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SWI_IRQn = 64, // *< Software interrupt
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RESERVED81_IRQn = 65, // *< Reserved interrupt 81
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RESERVED82_IRQn = 66, // *< Reserved interrupt 82
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RESERVED83_IRQn = 67, // *< Reserved interrupt 83
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RESERVED84_IRQn = 68, // *< Reserved interrupt 84
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RESERVED85_IRQn = 69, // *< Reserved interrupt 85
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RESERVED86_IRQn = 70, // *< Reserved interrupt 86
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FTM3_IRQn = 71, // *< FTM3 fault, overflow and channels interrupt
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DAC1_IRQn = 72, // *< DAC1 interrupt
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ADC1_IRQn = 73, // *< ADC1 interrupt
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RESERVED90_IRQn = 74, // *< Reserved Interrupt 90
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RESERVED91_IRQn = 75, // *< Reserved Interrupt 91
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RESERVED92_IRQn = 76, // *< Reserved Interrupt 92
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RESERVED93_IRQn = 77, // *< Reserved Interrupt 93
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RESERVED94_IRQn = 78, // *< Reserved Interrupt 94
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RESERVED95_IRQn = 79, // *< Reserved Interrupt 95
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RESERVED96_IRQn = 80, // *< Reserved Interrupt 96
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RESERVED97_IRQn = 81, // *< Reserved Interrupt 97
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RESERVED98_IRQn = 82, // *< Reserved Interrupt 98
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RESERVED99_IRQn = 83, // *< Reserved Interrupt 99
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RESERVED100_IRQn = 84, // *< Reserved Interrupt 100
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RESERVED101_IRQn = 85 // *< Reserved Interrupt 101
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);
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TADC_Registers = record
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SC1 : array[0..1] of longword; // *< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4
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CFG1 : longword; // *< ADC Configuration Register 1, offset: 0x8
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CFG2 : longword; // *< ADC Configuration Register 2, offset: 0xC
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R : array[0..1] of longword; // *< ADC Data Result Register, array offset: 0x10, array step: 0x4
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CV1 : longword; // *< Compare Value Registers, offset: 0x18
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CV2 : longword; // *< Compare Value Registers, offset: 0x1C
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SC2 : longword; // *< Status and Control Register 2, offset: 0x20
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SC3 : longword; // *< Status and Control Register 3, offset: 0x24
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OFS : longword; // *< ADC Offset Correction Register, offset: 0x28
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PG : longword; // *< ADC Plus-Side Gain Register, offset: 0x2C
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MG : longword; // *< ADC Minus-Side Gain Register, offset: 0x30
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CLPD : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x34
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CLPS : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x38
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CLP4 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x3C
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CLP3 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x40
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CLP2 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x44
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CLP1 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x48
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CLP0 : longword; // *< ADC Plus-Side General Calibration Value Register, offset: 0x4C
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RESERVED_0 : array[0..3] of byte;
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CLMD : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x54
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CLMS : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x58
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CLM4 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x5C
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CLM3 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x60
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CLM2 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x64
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CLM1 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x68
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CLM0 : longword; // *< ADC Minus-Side General Calibration Value Register, offset: 0x6C
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end;
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const
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ADC0_BASE = $4003B000;
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var
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ADC0 : TADC_Registers absolute ADC0_BASE;
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const
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ADC1_BASE = $40027000;
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var
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ADC1 : TADC_Registers absolute ADC1_BASE;
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type
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TCMP_Registers = record
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CR0 : byte; // *< CMP Control Register 0, offset: 0x0
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CR1 : byte; // *< CMP Control Register 1, offset: 0x1
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FPR : byte; // *< CMP Filter Period Register, offset: 0x2
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SCR : byte; // *< CMP Status and Control Register, offset: 0x3
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DACCR : byte; // *< DAC Control Register, offset: 0x4
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MUXCR : byte; // *< MUX Control Register, offset: 0x5
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end;
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const
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CMP0_BASE = $40073000;
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var
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CMP0 : TCMP_Registers absolute CMP0_BASE;
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const
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CMP1_BASE = $40073008;
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var
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CMP1 : TCMP_Registers absolute CMP1_BASE;
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type
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TCRC_Registers = record
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DATA : longword; // *< CRC Data register, offset: 0x0
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GPOLY : longword; // *< CRC Polynomial register, offset: 0x4
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CTRL : longword; // *< CRC Control register, offset: 0x8
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end;
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const
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CRC_BASE = $40032000;
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var
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CRC0 : TCRC_Registers absolute CRC_BASE;
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type
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TDAC_DAT = record
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DATL : byte; // *< DAC Data Low Register, array offset: 0x0, array step: 0x2
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DATH : byte; // *< DAC Data High Register, array offset: 0x1, array step: 0x2
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end;
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TDAC_Registers = record
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DAT : array[0..15] of TDAC_DAT;
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SR : byte; // *< DAC Status Register, offset: 0x20
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C0 : byte; // *< DAC Control Register, offset: 0x21
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C1 : byte; // *< DAC Control Register 1, offset: 0x22
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C2 : byte; // *< DAC Control Register 2, offset: 0x23
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end;
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const
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DAC0_BASE = $4003F000;
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var
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DAC0 : TDAC_Registers absolute DAC0_BASE;
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const
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DAC1_BASE = $40028000;
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var
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DAC1 : TDAC_Registers absolute DAC1_BASE;
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type
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TDMA_TCD = record
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SADDR : longword; // *< TCD Source Address, array offset: 0x1000, array step: 0x20
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SOFF : word; // *< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20
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ATTR : word; // *< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20
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NBYTES_MLNO: longword; // *< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20
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SLAST : longword; // *< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20
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DADDR : longword; // *< TCD Destination Address, array offset: 0x1010, array step: 0x20
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DOFF : word; // *< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20
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CITER_ELINKNO : word; // *< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20
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DLAST_SGA : longword; // *< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20
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CSR : word; // *< TCD Control and Status, array offset: 0x101C, array step: 0x20
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BITER_ELINKNO : word; // *< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20
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end;
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TDMA_Registers = record
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CR : longword; // *< Control Register, offset: 0x0
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ES : longword; // *< Error Status Register, offset: 0x4
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RESERVED_0 : array[0..3] of byte;
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ERQ : longword; // *< Enable Request Register, offset: 0xC
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RESERVED_1 : array[0..3] of byte;
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EEI : longword; // *< Enable Error Interrupt Register, offset: 0x14
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CEEI : byte; // *< Clear Enable Error Interrupt Register, offset: 0x18
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SEEI : byte; // *< Set Enable Error Interrupt Register, offset: 0x19
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CERQ : byte; // *< Clear Enable Request Register, offset: 0x1A
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SERQ : byte; // *< Set Enable Request Register, offset: 0x1B
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CDNE : byte; // *< Clear DONE Status Bit Register, offset: 0x1C
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SSRT : byte; // *< Set START Bit Register, offset: 0x1D
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CERR : byte; // *< Clear Error Register, offset: 0x1E
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CINT : byte; // *< Clear Interrupt Request Register, offset: 0x1F
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RESERVED_2 : array[0..3] of byte;
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INT : longword; // *< Interrupt Request Register, offset: 0x24
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RESERVED_3 : array[0..3] of byte;
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ERR : longword; // *< Error Register, offset: 0x2C
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RESERVED_4 : array[0..3] of byte;
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HRS : longword; // *< Hardware Request Status Register, offset: 0x34
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RESERVED_5 : array[0..11] of byte;
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EARS : longword; // *< Enable Asynchronous Request in Stop Register, offset: 0x44
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RESERVED_6 : array[0..183] of byte;
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DCHPRI3 : byte; // *< Channel n Priority Register, offset: 0x100
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DCHPRI2 : byte; // *< Channel n Priority Register, offset: 0x101
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DCHPRI1 : byte; // *< Channel n Priority Register, offset: 0x102
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DCHPRI0 : byte; // *< Channel n Priority Register, offset: 0x103
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DCHPRI7 : byte; // *< Channel n Priority Register, offset: 0x104
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DCHPRI6 : byte; // *< Channel n Priority Register, offset: 0x105
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DCHPRI5 : byte; // *< Channel n Priority Register, offset: 0x106
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DCHPRI4 : byte; // *< Channel n Priority Register, offset: 0x107
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DCHPRI11 : byte; // *< Channel n Priority Register, offset: 0x108
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DCHPRI10 : byte; // *< Channel n Priority Register, offset: 0x109
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DCHPRI9 : byte; // *< Channel n Priority Register, offset: 0x10A
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DCHPRI8 : byte; // *< Channel n Priority Register, offset: 0x10B
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DCHPRI15 : byte; // *< Channel n Priority Register, offset: 0x10C
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DCHPRI14 : byte; // *< Channel n Priority Register, offset: 0x10D
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DCHPRI13 : byte; // *< Channel n Priority Register, offset: 0x10E
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DCHPRI12 : byte; // *< Channel n Priority Register, offset: 0x10F
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RESERVED_7 : array[0..3823] of byte;
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TCD : array[0..15] of TDMA_TCD;
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end;
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const
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DMA_BASE = $40008000;
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var
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DMA0 : TDMA_Registers absolute DMA_BASE;
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type
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TDMAMUX_Registers = record
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CHCFG : array[0..15] of byte; // *< Channel Configuration register, array offset: 0x0, array step: 0x1
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end;
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const
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DMAMUX_BASE = $40021000;
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var
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DMAMUX : TDMAMUX_Registers absolute DMAMUX_BASE;
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type
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TEWM_Registers = record
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CTRL : byte; // *< Control Register, offset: 0x0
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SERV : byte; // *< Service Register, offset: 0x1
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CMPL : byte; // *< Compare Low Register, offset: 0x2
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CMPH : byte; // *< Compare High Register, offset: 0x3
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RESERVED_0 : array[0..0] of byte;
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CLKPRESCALER : byte; // *< Clock Prescaler Register, offset: 0x5
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end;
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const
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EWM_BASE = $40061000;
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var
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EWM : TEWM_Registers absolute EWM_BASE;
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type
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TFB_CS = record
|
|
CSAR : longword; // *< Chip Select Address Register, array offset: 0x0, array step: 0xC
|
|
CSMR : longword; // *< Chip Select Mask Register, array offset: 0x4, array step: 0xC
|
|
CSCR : longword; // *< Chip Select Control Register, array offset: 0x8, array step: 0xC
|
|
end;
|
|
|
|
TFB_Registers = record
|
|
CS : array[0..5] of TFB_CS;
|
|
RESERVED_0 : array[0..23] of byte;
|
|
CSPMCR : longword; // *< Chip Select port Multiplexing Control Register, offset: 0x60
|
|
end;
|
|
|
|
const
|
|
FB_BASE = $4000C000;
|
|
|
|
var
|
|
FB : TFB_Registers absolute FB_BASE;
|
|
|
|
type
|
|
TFMC_SET = record
|
|
DATA_U : longword; // *< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x40, index2*0x8
|
|
DATA_L : longword; // *< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x40, index2*0x8
|
|
end;
|
|
|
|
TFMC_Registers = record
|
|
PFAPR : longword; // *< Flash Access Protection Register, offset: 0x0
|
|
PFB0CR : longword; // *< Flash Bank 0 Control Register, offset: 0x4
|
|
PFB1CR : longword; // *< Flash Bank 1 Control Register, offset: 0x8
|
|
RESERVED_0 : array[0..243] of byte;
|
|
TAGVDW0S : array[0..7] of longword; // *< Cache Tag Storage, array offset: 0x100, array step: 0x4
|
|
TAGVDW1S : array[0..7] of longword; // *< Cache Tag Storage, array offset: 0x120, array step: 0x4
|
|
TAGVDW2S : array[0..7] of longword; // *< Cache Tag Storage, array offset: 0x140, array step: 0x4
|
|
TAGVDW3S : array[0..7] of longword; // *< Cache Tag Storage, array offset: 0x160, array step: 0x4
|
|
RESERVED_1 : array[0..127] of byte;
|
|
&SET : array[0..3] of TFMC_SET;
|
|
end;
|
|
|
|
const
|
|
FMC_BASE = $4001F000;
|
|
|
|
var
|
|
FMC : TFMC_Registers absolute FMC_BASE;
|
|
|
|
type
|
|
TFTFA_Registers = record
|
|
FSTAT : byte; // *< Flash Status Register, offset: 0x0
|
|
FCNFG : byte; // *< Flash Configuration Register, offset: 0x1
|
|
FSEC : byte; // *< Flash Security Register, offset: 0x2
|
|
FOPT : byte; // *< Flash Option Register, offset: 0x3
|
|
FCCOB3 : byte; // *< Flash Common Command Object Registers, offset: 0x4
|
|
FCCOB2 : byte; // *< Flash Common Command Object Registers, offset: 0x5
|
|
FCCOB1 : byte; // *< Flash Common Command Object Registers, offset: 0x6
|
|
FCCOB0 : byte; // *< Flash Common Command Object Registers, offset: 0x7
|
|
FCCOB7 : byte; // *< Flash Common Command Object Registers, offset: 0x8
|
|
FCCOB6 : byte; // *< Flash Common Command Object Registers, offset: 0x9
|
|
FCCOB5 : byte; // *< Flash Common Command Object Registers, offset: 0xA
|
|
FCCOB4 : byte; // *< Flash Common Command Object Registers, offset: 0xB
|
|
FCCOBB : byte; // *< Flash Common Command Object Registers, offset: 0xC
|
|
FCCOBA : byte; // *< Flash Common Command Object Registers, offset: 0xD
|
|
FCCOB9 : byte; // *< Flash Common Command Object Registers, offset: 0xE
|
|
FCCOB8 : byte; // *< Flash Common Command Object Registers, offset: 0xF
|
|
FPROT3 : byte; // *< Program Flash Protection Registers, offset: 0x10
|
|
FPROT2 : byte; // *< Program Flash Protection Registers, offset: 0x11
|
|
FPROT1 : byte; // *< Program Flash Protection Registers, offset: 0x12
|
|
FPROT0 : byte; // *< Program Flash Protection Registers, offset: 0x13
|
|
RESERVED_0 : array[0..3] of byte;
|
|
XACCH3 : byte; // *< Execute-only Access Registers, offset: 0x18
|
|
XACCH2 : byte; // *< Execute-only Access Registers, offset: 0x19
|
|
XACCH1 : byte; // *< Execute-only Access Registers, offset: 0x1A
|
|
XACCH0 : byte; // *< Execute-only Access Registers, offset: 0x1B
|
|
XACCL3 : byte; // *< Execute-only Access Registers, offset: 0x1C
|
|
XACCL2 : byte; // *< Execute-only Access Registers, offset: 0x1D
|
|
XACCL1 : byte; // *< Execute-only Access Registers, offset: 0x1E
|
|
XACCL0 : byte; // *< Execute-only Access Registers, offset: 0x1F
|
|
SACCH3 : byte; // *< Supervisor-only Access Registers, offset: 0x20
|
|
SACCH2 : byte; // *< Supervisor-only Access Registers, offset: 0x21
|
|
SACCH1 : byte; // *< Supervisor-only Access Registers, offset: 0x22
|
|
SACCH0 : byte; // *< Supervisor-only Access Registers, offset: 0x23
|
|
SACCL3 : byte; // *< Supervisor-only Access Registers, offset: 0x24
|
|
SACCL2 : byte; // *< Supervisor-only Access Registers, offset: 0x25
|
|
SACCL1 : byte; // *< Supervisor-only Access Registers, offset: 0x26
|
|
SACCL0 : byte; // *< Supervisor-only Access Registers, offset: 0x27
|
|
FACSS : byte; // *< Flash Access Segment Size Register, offset: 0x28
|
|
RESERVED_1 : array[0..1] of byte;
|
|
FACSN : byte; // *< Flash Access Segment Number Register, offset: 0x2B
|
|
end;
|
|
|
|
const
|
|
FTFA_BASE = $40020000;
|
|
|
|
var
|
|
FTFA : TFTFA_Registers absolute FTFA_BASE;
|
|
|
|
type
|
|
TFMT_CONTROLS = record
|
|
CnSC : longword; // *< Channel (n) Status And Control, array offset: 0xC, array step: 0x8
|
|
CnV : longword; // *< Channel (n) Value, array offset: 0x10, array step: 0x8
|
|
end;
|
|
|
|
TFTM_Registers = record
|
|
SC : longword; // *< Status And Control, offset: 0x0
|
|
CNT : longword; // *< Counter, offset: 0x4
|
|
&MOD : longword; // *< Modulo, offset: 0x8
|
|
CONTROLS : array[0..7] of TFMT_CONTROLS;
|
|
CNTIN : longword; // *< Counter Initial Value, offset: 0x4C
|
|
STATUS : longword; // *< Capture And Compare Status, offset: 0x50
|
|
MODE : longword; // *< Features Mode Selection, offset: 0x54
|
|
SYNC : longword; // *< Synchronization, offset: 0x58
|
|
OUTINIT : longword; // *< Initial State For Channels Output, offset: 0x5C
|
|
OUTMASK : longword; // *< Output Mask, offset: 0x60
|
|
COMBINE : longword; // *< Function For Linked Channels, offset: 0x64
|
|
DEADTIME : longword; // *< Deadtime Insertion Control, offset: 0x68
|
|
EXTTRIG : longword; // *< FTM External Trigger, offset: 0x6C
|
|
POL : longword; // *< Channels Polarity, offset: 0x70
|
|
FMS : longword; // *< Fault Mode Status, offset: 0x74
|
|
FILTER : longword; // *< Input Capture Filter Control, offset: 0x78
|
|
FLTCTRL : longword; // *< Fault Control, offset: 0x7C
|
|
QDCTRL : longword; // *< Quadrature Decoder Control And Status, offset: 0x80
|
|
CONF : longword; // *< Configuration, offset: 0x84
|
|
FLTPOL : longword; // *< FTM Fault Input Polarity, offset: 0x88
|
|
SYNCONF : longword; // *< Synchronization Configuration, offset: 0x8C
|
|
INVCTRL : longword; // *< FTM Inverting Control, offset: 0x90
|
|
SWOCTRL : longword; // *< FTM Software Output Control, offset: 0x94
|
|
PWMLOAD : longword; // *< FTM PWM Load, offset: 0x98
|
|
end;
|
|
|
|
const
|
|
FTM0_BASE = $40038000;
|
|
|
|
var
|
|
FTM0 : TFTM_Registers absolute FTM0_BASE;
|
|
|
|
const
|
|
FTM1_BASE = $40039000;
|
|
|
|
var
|
|
FTM1 : TFTM_Registers absolute FTM1_BASE;
|
|
|
|
const
|
|
FTM2_BASE = $4003A000;
|
|
|
|
var
|
|
FTM2 : TFTM_Registers absolute FTM2_BASE;
|
|
|
|
const
|
|
FTM3_BASE = $40026000;
|
|
|
|
var
|
|
FTM3 : TFTM_Registers absolute FTM3_BASE;
|
|
|
|
type
|
|
TGPIO_Registers = record
|
|
PDOR : longword; // *< Port Data Output Register, offset: 0x0
|
|
PSOR : longword; // *< Port Set Output Register, offset: 0x4
|
|
PCOR : longword; // *< Port Clear Output Register, offset: 0x8
|
|
PTOR : longword; // *< Port Toggle Output Register, offset: 0xC
|
|
PDIR : longword; // *< Port Data Input Register, offset: 0x10
|
|
PDDR : longword; // *< Port Data Direction Register, offset: 0x14
|
|
end;
|
|
|
|
const
|
|
PTA_BASE = $400FF000;
|
|
|
|
var
|
|
PTA : TGPIO_Registers absolute PTA_BASE;
|
|
|
|
const
|
|
PTB_BASE = $400FF040;
|
|
|
|
var
|
|
PTB : TGPIO_Registers absolute PTB_BASE;
|
|
|
|
const
|
|
PTC_BASE = $400FF080;
|
|
|
|
var
|
|
PTC : TGPIO_Registers absolute PTC_BASE;
|
|
|
|
const
|
|
PTD_BASE = $400FF0C0;
|
|
|
|
var
|
|
PTD : TGPIO_Registers absolute PTD_BASE;
|
|
|
|
const
|
|
PTE_BASE = $400FF100;
|
|
|
|
var
|
|
PTE : TGPIO_Registers absolute PTE_BASE;
|
|
|
|
type
|
|
TI2C_Registers = record
|
|
A1 : byte; // *< I2C Address Register 1, offset: 0x0
|
|
F : byte; // *< I2C Frequency Divider register, offset: 0x1
|
|
C1 : byte; // *< I2C Control Register 1, offset: 0x2
|
|
S : byte; // *< I2C Status register, offset: 0x3
|
|
D : byte; // *< I2C Data I/O register, offset: 0x4
|
|
C2 : byte; // *< I2C Control Register 2, offset: 0x5
|
|
FLT : byte; // *< I2C Programmable Input Glitch Filter register, offset: 0x6
|
|
RA : byte; // *< I2C Range Address register, offset: 0x7
|
|
SMB : byte; // *< I2C SMBus Control and Status register, offset: 0x8
|
|
A2 : byte; // *< I2C Address Register 2, offset: 0x9
|
|
SLTH : byte; // *< I2C SCL Low Timeout Register High, offset: 0xA
|
|
SLTL : byte; // *< I2C SCL Low Timeout Register Low, offset: 0xB
|
|
end;
|
|
|
|
const
|
|
I2C0_BASE = $40066000;
|
|
|
|
var
|
|
I2C0 : TI2C_Registers absolute I2C0_BASE;
|
|
|
|
const
|
|
I2C1_BASE = $40067000;
|
|
|
|
var
|
|
I2C1 : TI2C_Registers absolute I2C1_BASE;
|
|
|
|
type
|
|
TI2S_Registers = record
|
|
TCSR : longword; // *< SAI Transmit Control Register, offset: 0x0
|
|
TCR1 : longword; // *< SAI Transmit Configuration 1 Register, offset: 0x4
|
|
TCR2 : longword; // *< SAI Transmit Configuration 2 Register, offset: 0x8
|
|
TCR3 : longword; // *< SAI Transmit Configuration 3 Register, offset: 0xC
|
|
TCR4 : longword; // *< SAI Transmit Configuration 4 Register, offset: 0x10
|
|
TCR5 : longword; // *< SAI Transmit Configuration 5 Register, offset: 0x14
|
|
RESERVED_0 : array[0..7] of byte;
|
|
TDR : longWord; // *< SAI Transmit Data Register, array offset: 0x20, array step: 0x4
|
|
RESERVED_1 : array[0..27] of byte;
|
|
TFR : longWord; // *< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4
|
|
RESERVED_2 : array[0..27] of byte;
|
|
TMR : longword; // *< SAI Transmit Mask Register, offset: 0x60
|
|
RESERVED_3 : array[0..27] of byte;
|
|
RCSR : longword; // *< SAI Receive Control Register, offset: 0x80
|
|
RCR1 : longword; // *< SAI Receive Configuration 1 Register, offset: 0x84
|
|
RCR2 : longword; // *< SAI Receive Configuration 2 Register, offset: 0x88
|
|
RCR3 : longword; // *< SAI Receive Configuration 3 Register, offset: 0x8C
|
|
RCR4 : longword; // *< SAI Receive Configuration 4 Register, offset: 0x90
|
|
RCR5 : longword; // *< SAI Receive Configuration 5 Register, offset: 0x94
|
|
RESERVED_4 : array[0..7] of byte;
|
|
RDR : longWord; // *< SAI Receive Data Register, array offset: 0xA0, array step: 0x4
|
|
RESERVED_5 : array[0..27] of byte;
|
|
RFR : longWord; // *< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4
|
|
RESERVED_6 : array[0..27] of byte;
|
|
RMR : longword; // *< SAI Receive Mask Register, offset: 0xE0
|
|
RESERVED_7 : array[0..27] of byte;
|
|
MCR : longword; // *< SAI MCLK Control Register, offset: 0x100
|
|
MDR : longword; // *< SAI MCLK Divide Register, offset: 0x104
|
|
end;
|
|
|
|
const
|
|
I2S0_BASE = $4002F000;
|
|
|
|
var
|
|
I2S0 : TI2S_Registers absolute I2S0_BASE;
|
|
|
|
type
|
|
TLLWU_Registers = record
|
|
PE1 : byte; // *< LLWU Pin Enable 1 register, offset: 0x0
|
|
PE2 : byte; // *< LLWU Pin Enable 2 register, offset: 0x1
|
|
PE3 : byte; // *< LLWU Pin Enable 3 register, offset: 0x2
|
|
PE4 : byte; // *< LLWU Pin Enable 4 register, offset: 0x3
|
|
ME : byte; // *< LLWU Module Enable register, offset: 0x4
|
|
F1 : byte; // *< LLWU Flag 1 register, offset: 0x5
|
|
F2 : byte; // *< LLWU Flag 2 register, offset: 0x6
|
|
F3 : byte; // *< LLWU Flag 3 register, offset: 0x7
|
|
FILT1 : byte; // *< LLWU Pin Filter 1 register, offset: 0x8
|
|
FILT2 : byte; // *< LLWU Pin Filter 2 register, offset: 0x9
|
|
end;
|
|
|
|
const
|
|
LLWU_BASE = $4007C000;
|
|
|
|
var
|
|
LLWU : TLLWU_Registers absolute LLWU_BASE;
|
|
|
|
type
|
|
TLPTMR_Registers = record
|
|
CSR : longword; // *< Low Power Timer Control Status Register, offset: 0x0
|
|
PSR : longword; // *< Low Power Timer Prescale Register, offset: 0x4
|
|
CMR : longword; // *< Low Power Timer Compare Register, offset: 0x8
|
|
CNR : longword; // *< Low Power Timer Counter Register, offset: 0xC
|
|
end;
|
|
|
|
const
|
|
LPTMR0_BASE = $40040000;
|
|
|
|
var
|
|
LPTMR0 : TLPTMR_Registers absolute LPTMR0_BASE;
|
|
|
|
type
|
|
TLPUART_Registers = record
|
|
BAUD : longword; // *< LPUART Baud Rate Register, offset: 0x0
|
|
STAT : longword; // *< LPUART Status Register, offset: 0x4
|
|
CTRL : longword; // *< LPUART Control Register, offset: 0x8
|
|
DATA : longword; // *< LPUART Data Register, offset: 0xC
|
|
MATCH : longword; // *< LPUART Match Address Register, offset: 0x10
|
|
MODIR : longword; // *< LPUART Modem IrDA Register, offset: 0x14
|
|
end;
|
|
|
|
const
|
|
LPUART0_BASE = $4002A000;
|
|
|
|
var
|
|
LPUART0 : TLPUART_Registers absolute LPUART0_BASE;
|
|
|
|
type
|
|
TMCG_Registers = record
|
|
C1 : byte; // *< MCG Control 1 Register, offset: 0x0
|
|
C2 : byte; // *< MCG Control 2 Register, offset: 0x1
|
|
C3 : byte; // *< MCG Control 3 Register, offset: 0x2
|
|
C4 : byte; // *< MCG Control 4 Register, offset: 0x3
|
|
C5 : byte; // *< MCG Control 5 Register, offset: 0x4
|
|
C6 : byte; // *< MCG Control 6 Register, offset: 0x5
|
|
S : byte; // *< MCG Status Register, offset: 0x6
|
|
RESERVED_0 : array[0..0] of byte;
|
|
SC : byte; // *< MCG Status and Control Register, offset: 0x8
|
|
RESERVED_1 : array[0..0] of byte;
|
|
ATCVH : byte; // *< MCG Auto Trim Compare Value High Register, offset: 0xA
|
|
ATCVL : byte; // *< MCG Auto Trim Compare Value Low Register, offset: 0xB
|
|
C7 : byte; // *< MCG Control 7 Register, offset: 0xC
|
|
C8 : byte; // *< MCG Control 8 Register, offset: 0xD
|
|
end;
|
|
|
|
const
|
|
MCG_BASE = $40064000;
|
|
|
|
var
|
|
MCG : TMCG_Registers absolute MCG_BASE;
|
|
|
|
type
|
|
TMCM_Registers = record
|
|
RESERVED_0 : array[0..7] of byte;
|
|
PLASC : word; // *< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8
|
|
PLAMC : word; // *< Crossbar Switch (AXBS) Master Configuration, offset: 0xA
|
|
PLACR : longword; // *< Crossbar Switch (AXBS) Control Register, offset: 0xC
|
|
ISR : longword; // *< Interrupt Status and Control Register, offset: 0x10
|
|
RESERVED_1 : array[0..43] of byte;
|
|
CPO : longword; // *< Compute Operation Control Register, offset: 0x40
|
|
end;
|
|
|
|
const
|
|
MCM_BASE = $E0080000;
|
|
|
|
var
|
|
MCM : TMCM_Registers absolute MCM_BASE;
|
|
|
|
type
|
|
TNV_Registers = record
|
|
BACKKEY3 : byte; // *< Backdoor Comparison Key 3., offset: 0x0
|
|
BACKKEY2 : byte; // *< Backdoor Comparison Key 2., offset: 0x1
|
|
BACKKEY1 : byte; // *< Backdoor Comparison Key 1., offset: 0x2
|
|
BACKKEY0 : byte; // *< Backdoor Comparison Key 0., offset: 0x3
|
|
BACKKEY7 : byte; // *< Backdoor Comparison Key 7., offset: 0x4
|
|
BACKKEY6 : byte; // *< Backdoor Comparison Key 6., offset: 0x5
|
|
BACKKEY5 : byte; // *< Backdoor Comparison Key 5., offset: 0x6
|
|
BACKKEY4 : byte; // *< Backdoor Comparison Key 4., offset: 0x7
|
|
FPROT3 : byte; // *< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8
|
|
FPROT2 : byte; // *< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9
|
|
FPROT1 : byte; // *< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA
|
|
FPROT0 : byte; // *< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB
|
|
FSEC : byte; // *< Non-volatile Flash Security Register, offset: 0xC
|
|
FOPT : byte; // *< Non-volatile Flash Option Register, offset: 0xD
|
|
end;
|
|
|
|
const
|
|
FTFA_FlashConfig_BASE = $400;
|
|
|
|
var
|
|
FTFA_FlashConfig : TNV_Registers absolute FTFA_FlashConfig_BASE;
|
|
|
|
type
|
|
TOSC_Registers = record
|
|
CR : byte; // *< OSC Control Register, offset: 0x0
|
|
RESERVED_0 : array[0..0] of byte;
|
|
&DIV : byte; // *< OSC_DIV, offset: 0x2
|
|
end;
|
|
|
|
const
|
|
OSC_BASE = $40065000;
|
|
|
|
var
|
|
OSC : TOSC_Registers absolute OSC_BASE;
|
|
|
|
type
|
|
TPDB_CH = record
|
|
C1 : longword; // *< Channel n Control register 1, array offset: 0x10, array step: 0x28
|
|
S : longword; // *< Channel n Status register, array offset: 0x14, array step: 0x28
|
|
DLY : array[0..1] of longword; // *< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4
|
|
RESERVED_0 : array[0..23] of byte;
|
|
end;
|
|
TPDB_DAC = record
|
|
INTC : longword; // *< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8
|
|
INT : longword; // *< DAC Interval n register, array offset: 0x154, array step: 0x8
|
|
end;
|
|
|
|
TPDB_Registers = record
|
|
SC : longword; // *< Status and Control register, offset: 0x0
|
|
&MOD : longword; // *< Modulus register, offset: 0x4
|
|
CNT : longword; // *< Counter register, offset: 0x8
|
|
IDLY : longword; // *< Interrupt Delay register, offset: 0xC
|
|
CH : array[0..1] of TPDB_CH;
|
|
RESERVED_0 : array[0..239] of byte;
|
|
DAC : array[0..1] of TPDB_DAC;
|
|
RESERVED_1 : array[0..47] of byte;
|
|
POEN : longword; // *< Pulse-Out n Enable register, offset: 0x190
|
|
PODLY : array[0..1] of longword; // *< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4
|
|
end;
|
|
|
|
const
|
|
PDB0_BASE = $40036000;
|
|
|
|
var
|
|
PDB0 : TPDB_Registers absolute PDB0_BASE;
|
|
|
|
type
|
|
TPIT_CHANNEL = record
|
|
LDVAL : longword; // *< Timer Load Value Register, array offset: 0x100, array step: 0x10
|
|
CVAL : longword; // *< Current Timer Value Register, array offset: 0x104, array step: 0x10
|
|
TCTRL : longword; // *< Timer Control Register, array offset: 0x108, array step: 0x10
|
|
TFLG : longword; // *< Timer Flag Register, array offset: 0x10C, array step: 0x10
|
|
end;
|
|
|
|
TPIT_Registers = record
|
|
MCR : longword; // *< PIT Module Control Register, offset: 0x0
|
|
RESERVED_0 : array[0..251] of byte;
|
|
CHANNEL : array[0..3] of TPIT_CHANNEL;
|
|
end;
|
|
|
|
const
|
|
PIT_BASE = $40037000;
|
|
|
|
var
|
|
PIT : TPIT_Registers absolute PIT_BASE;
|
|
|
|
type
|
|
TPMC_Registers = record
|
|
LVDSC1 : byte; // *< Low Voltage Detect Status And Control 1 register, offset: 0x0
|
|
LVDSC2 : byte; // *< Low Voltage Detect Status And Control 2 register, offset: 0x1
|
|
REGSC : byte; // *< Regulator Status And Control register, offset: 0x2
|
|
end;
|
|
|
|
const
|
|
PMC_BASE = $4007D000;
|
|
|
|
var
|
|
PMC : TPMC_Registers absolute PMC_BASE;
|
|
|
|
type
|
|
TPORT_Registers = record
|
|
PCR : array[0..31] of longword; // *< Pin Control Register n, array offset: 0x0, array step: 0x4
|
|
GPCLR : longword; // *< Global Pin Control Low Register, offset: 0x80
|
|
GPCHR : longword; // *< Global Pin Control High Register, offset: 0x84
|
|
RESERVED_0 : array[0..23] of byte;
|
|
ISFR : longword; // *< Interrupt Status Flag Register, offset: 0xA0
|
|
RESERVED_1 : array[0..27] of byte;
|
|
DFER : longword; // *< Digital Filter Enable Register, offset: 0xC0
|
|
DFCR : longword; // *< Digital Filter Clock Register, offset: 0xC4
|
|
DFWR : longword; // *< Digital Filter Width Register, offset: 0xC8
|
|
end;
|
|
|
|
const
|
|
PORTA_BASE = $40049000;
|
|
|
|
var
|
|
PORTA : TPORT_Registers absolute PORTA_BASE;
|
|
|
|
const
|
|
PORTB_BASE = $4004A000;
|
|
|
|
var
|
|
PORTB : TPORT_Registers absolute PORTB_BASE;
|
|
|
|
const
|
|
PORTC_BASE = $4004B000;
|
|
|
|
var
|
|
PORTC : TPORT_Registers absolute PORTC_BASE;
|
|
|
|
const
|
|
PORTD_BASE = $4004C000;
|
|
|
|
var
|
|
PORTD : TPORT_Registers absolute PORTD_BASE;
|
|
|
|
const
|
|
PORTE_BASE = $4004D000;
|
|
|
|
var
|
|
PORTE : TPORT_Registers absolute PORTE_BASE;
|
|
|
|
type
|
|
TRCM_Registers = record
|
|
SRS0 : byte; // *< System Reset Status Register 0, offset: 0x0
|
|
SRS1 : byte; // *< System Reset Status Register 1, offset: 0x1
|
|
RESERVED_0 : array[0..1] of byte;
|
|
RPFC : byte; // *< Reset Pin Filter Control register, offset: 0x4
|
|
RPFW : byte; // *< Reset Pin Filter Width register, offset: 0x5
|
|
RESERVED_1 : array[0..0] of byte;
|
|
MR : byte; // *< Mode Register, offset: 0x7
|
|
SSRS0 : byte; // *< Sticky System Reset Status Register 0, offset: 0x8
|
|
SSRS1 : byte; // *< Sticky System Reset Status Register 1, offset: 0x9
|
|
end;
|
|
|
|
const
|
|
RCM_BASE = $4007F000;
|
|
|
|
var
|
|
RCM : TRCM_Registers absolute RCM_BASE;
|
|
|
|
type
|
|
TRFSYS_Registers = record
|
|
REG : array[0..7] of longword; // *< Register file register, array offset: 0x0, array step: 0x4
|
|
end;
|
|
|
|
const
|
|
RFSYS_BASE = $40041000;
|
|
|
|
var
|
|
RFSYS : TRFSYS_Registers absolute RFSYS_BASE;
|
|
|
|
type
|
|
TRFVBAT_Registers = record
|
|
REG : array[0..7] of longword; // *< VBAT register file register, array offset: 0x0, array step: 0x4
|
|
end;
|
|
|
|
const
|
|
RFVBAT_BASE = $4003E000;
|
|
|
|
var
|
|
RFVBAT : TRFVBAT_Registers absolute RFVBAT_BASE;
|
|
|
|
type
|
|
TRNG_Registers = record
|
|
CR : longword; // *< RNGA Control Register, offset: 0x0
|
|
SR : longword; // *< RNGA Status Register, offset: 0x4
|
|
ER : longword; // *< RNGA Entropy Register, offset: 0x8
|
|
&OR : longword; // *< RNGA Output Register, offset: 0xC
|
|
end;
|
|
|
|
const
|
|
RNG_BASE = $40029000;
|
|
|
|
var
|
|
RNG : TRNG_Registers absolute RNG_BASE;
|
|
|
|
type
|
|
TRTC_Registers = record
|
|
TSR : longword; // *< RTC Time Seconds Register, offset: 0x0
|
|
TPR : longword; // *< RTC Time Prescaler Register, offset: 0x4
|
|
TAR : longword; // *< RTC Time Alarm Register, offset: 0x8
|
|
TCR : longword; // *< RTC Time Compensation Register, offset: 0xC
|
|
CR : longword; // *< RTC Control Register, offset: 0x10
|
|
SR : longword; // *< RTC Status Register, offset: 0x14
|
|
LR : longword; // *< RTC Lock Register, offset: 0x18
|
|
IER : longword; // *< RTC Interrupt Enable Register, offset: 0x1C
|
|
RESERVED_0 : array[0..2015] of byte;
|
|
WAR : longword; // *< RTC Write Access Register, offset: 0x800
|
|
RAR : longword; // *< RTC Read Access Register, offset: 0x804
|
|
end;
|
|
|
|
const
|
|
RTC_BASE = $4003D000;
|
|
|
|
var
|
|
RTC : TRTC_Registers absolute RTC_BASE;
|
|
|
|
type
|
|
TSIM_Registers = record
|
|
SOPT1 : longword; // *< System Options Register 1, offset: 0x0
|
|
SOPT1CFG : longword; // *< SOPT1 Configuration Register, offset: 0x4
|
|
RESERVED_0 : array[0..4091] of byte;
|
|
SOPT2 : longword; // *< System Options Register 2, offset: 0x1004
|
|
RESERVED_1 : array[0..3] of byte;
|
|
SOPT4 : longword; // *< System Options Register 4, offset: 0x100C
|
|
SOPT5 : longword; // *< System Options Register 5, offset: 0x1010
|
|
RESERVED_2 : array[0..3] of byte;
|
|
SOPT7 : longword; // *< System Options Register 7, offset: 0x1018
|
|
SOPT8 : longword; // *< System Options Register 8, offset: 0x101C
|
|
RESERVED_3 : array[0..3] of byte;
|
|
SDID : longword; // *< System Device Identification Register, offset: 0x1024
|
|
RESERVED_4 : array[0..11] of byte;
|
|
SCGC4 : longword; // *< System Clock Gating Control Register 4, offset: 0x1034
|
|
SCGC5 : longword; // *< System Clock Gating Control Register 5, offset: 0x1038
|
|
SCGC6 : longword; // *< System Clock Gating Control Register 6, offset: 0x103C
|
|
SCGC7 : longword; // *< System Clock Gating Control Register 7, offset: 0x1040
|
|
CLKDIV1 : longword; // *< System Clock Divider Register 1, offset: 0x1044
|
|
CLKDIV2 : longword; // *< System Clock Divider Register 2, offset: 0x1048
|
|
FCFG1 : longword; // *< Flash Configuration Register 1, offset: 0x104C
|
|
FCFG2 : longword; // *< Flash Configuration Register 2, offset: 0x1050
|
|
UIDH : longword; // *< Unique Identification Register High, offset: 0x1054
|
|
UIDMH : longword; // *< Unique Identification Register Mid-High, offset: 0x1058
|
|
UIDML : longword; // *< Unique Identification Register Mid Low, offset: 0x105C
|
|
UIDL : longword; // *< Unique Identification Register Low, offset: 0x1060
|
|
end;
|
|
|
|
const
|
|
SIM_BASE = $40047000;
|
|
|
|
var
|
|
SIM : TSIM_Registers absolute SIM_BASE;
|
|
|
|
type
|
|
TSMC_Registers = record
|
|
PMPROT : byte; // *< Power Mode Protection register, offset: 0x0
|
|
PMCTRL : byte; // *< Power Mode Control register, offset: 0x1
|
|
STOPCTRL : byte; // *< Stop Control Register, offset: 0x2
|
|
PMSTAT : byte; // *< Power Mode Status register, offset: 0x3
|
|
end;
|
|
|
|
const
|
|
SMC_BASE = $4007E000;
|
|
|
|
var
|
|
SMC : TSMC_Registers absolute SMC_BASE;
|
|
|
|
type
|
|
TSPI_Registers = record
|
|
MCR : longword; // *< Module Configuration Register, offset: 0x0
|
|
RESERVED_0 : array[0..3] of byte;
|
|
TCR : longword; // *< Transfer Count Register, offset: 0x8
|
|
CTAR : array[0..1] of longword; // *< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4
|
|
RESERVED_1 : array[0..23] of byte;
|
|
SR : longword; // *< Status Register, offset: 0x2C
|
|
RSER : longword; // *< DMA/Interrupt Request Select and Enable Register, offset: 0x30
|
|
PUSHR : longword; // *< PUSH TX FIFO Register In Master Mode, offset: 0x34
|
|
POPR : longword; // *< POP RX FIFO Register, offset: 0x38
|
|
TXFR0 : longword; // *< Transmit FIFO Registers, offset: 0x3C
|
|
TXFR1 : longword; // *< Transmit FIFO Registers, offset: 0x40
|
|
TXFR2 : longword; // *< Transmit FIFO Registers, offset: 0x44
|
|
TXFR3 : longword; // *< Transmit FIFO Registers, offset: 0x48
|
|
RESERVED_2 : array[0..47] of byte;
|
|
RXFR0 : longword; // *< Receive FIFO Registers, offset: 0x7C
|
|
RXFR1 : longword; // *< Receive FIFO Registers, offset: 0x80
|
|
RXFR2 : longword; // *< Receive FIFO Registers, offset: 0x84
|
|
RXFR3 : longword; // *< Receive FIFO Registers, offset: 0x88
|
|
end;
|
|
|
|
const
|
|
SPI0_BASE = $4002C000;
|
|
|
|
var
|
|
SPI0 : TSPI_Registers absolute SPI0_BASE;
|
|
|
|
const
|
|
SPI1_BASE = $4002D000;
|
|
|
|
var
|
|
SPI1 : TSPI_Registers absolute SPI1_BASE;
|
|
|
|
type
|
|
TUART_Registers = record
|
|
BDH : byte; // *< UART Baud Rate Registers: High, offset: 0x0
|
|
BDL : byte; // *< UART Baud Rate Registers: Low, offset: 0x1
|
|
C1 : byte; // *< UART Control Register 1, offset: 0x2
|
|
C2 : byte; // *< UART Control Register 2, offset: 0x3
|
|
S1 : byte; // *< UART Status Register 1, offset: 0x4
|
|
S2 : byte; // *< UART Status Register 2, offset: 0x5
|
|
C3 : byte; // *< UART Control Register 3, offset: 0x6
|
|
D : byte; // *< UART Data Register, offset: 0x7
|
|
MA1 : byte; // *< UART Match Address Registers 1, offset: 0x8
|
|
MA2 : byte; // *< UART Match Address Registers 2, offset: 0x9
|
|
C4 : byte; // *< UART Control Register 4, offset: 0xA
|
|
C5 : byte; // *< UART Control Register 5, offset: 0xB
|
|
ED : byte; // *< UART Extended Data Register, offset: 0xC
|
|
MODEM : byte; // *< UART Modem Register, offset: 0xD
|
|
IR : byte; // *< UART Infrared Register, offset: 0xE
|
|
RESERVED_0 : array[0..0] of byte;
|
|
PFIFO : byte; // *< UART FIFO Parameters, offset: 0x10
|
|
CFIFO : byte; // *< UART FIFO Control Register, offset: 0x11
|
|
SFIFO : byte; // *< UART FIFO Status Register, offset: 0x12
|
|
TWFIFO : byte; // *< UART FIFO Transmit Watermark, offset: 0x13
|
|
TCFIFO : byte; // *< UART FIFO Transmit Count, offset: 0x14
|
|
RWFIFO : byte; // *< UART FIFO Receive Watermark, offset: 0x15
|
|
RCFIFO : byte; // *< UART FIFO Receive Count, offset: 0x16
|
|
RESERVED_1 : array[0..0] of byte;
|
|
C7816 : byte; // *< UART 7816 Control Register, offset: 0x18
|
|
IE7816 : byte; // *< UART 7816 Interrupt Enable Register, offset: 0x19
|
|
IS7816 : byte; // *< UART 7816 Interrupt Status Register, offset: 0x1A
|
|
WP7816 : byte; // *< UART 7816 Wait Parameter Register, offset: 0x1B
|
|
WN7816 : byte; // *< UART 7816 Wait N Register, offset: 0x1C
|
|
WF7816 : byte; // *< UART 7816 Wait FD Register, offset: 0x1D
|
|
ET7816 : byte; // *< UART 7816 Error Threshold Register, offset: 0x1E
|
|
TL7816 : byte; // *< UART 7816 Transmit Length Register, offset: 0x1F
|
|
RESERVED_2 : array[0..25] of byte;
|
|
AP7816A_T0 : byte; // *< UART 7816 ATR Duration Timer Register A, offset: 0x3A
|
|
AP7816B_T0 : byte; // *< UART 7816 ATR Duration Timer Register B, offset: 0x3B
|
|
WP7816A_T0 : byte; // *< UART 7816 Wait Parameter Register A, offset: 0x3C
|
|
WP7816B_T0 : byte; // *< UART 7816 Wait Parameter Register B, offset: 0x3D
|
|
WGP7816_T1 : byte; // *< UART 7816 Wait and Guard Parameter Register, offset: 0x3E
|
|
WP7816C_T1 : byte; // *< UART 7816 Wait Parameter Register C, offset: 0x3F
|
|
end;
|
|
|
|
const
|
|
UART0_BASE = $4006A000;
|
|
|
|
var
|
|
UART0 : TUART_Registers absolute UART0_BASE;
|
|
|
|
const
|
|
UART1_BASE = $4006B000;
|
|
|
|
var
|
|
UART1 : TUART_Registers absolute UART1_BASE;
|
|
|
|
const
|
|
UART2_BASE = $4006C000;
|
|
|
|
var
|
|
UART2 : TUART_Registers absolute UART2_BASE;
|
|
|
|
type
|
|
TUSB_ENDPOINT= record
|
|
ENDPT : byte; // *< Endpoint Control register, array offset: 0xC0, array step: 0x4
|
|
RESERVED_0 : array[0..2] of byte;
|
|
end;
|
|
|
|
TUSB_Registers = record
|
|
PERID : byte; // *< Peripheral ID register, offset: 0x0
|
|
RESERVED_0 : array[0..2] of byte;
|
|
IDCOMP : byte; // *< Peripheral ID Complement register, offset: 0x4
|
|
RESERVED_1 : array[0..2] of byte;
|
|
REV : byte; // *< Peripheral Revision register, offset: 0x8
|
|
RESERVED_2 : array[0..2] of byte;
|
|
ADDINFO : byte; // *< Peripheral Additional Info register, offset: 0xC
|
|
RESERVED_3 : array[0..2] of byte;
|
|
OTGISTAT : byte; // *< OTG Interrupt Status register, offset: 0x10
|
|
RESERVED_4 : array[0..2] of byte;
|
|
OTGICR : byte; // *< OTG Interrupt Control register, offset: 0x14
|
|
RESERVED_5 : array[0..2] of byte;
|
|
OTGSTAT : byte; // *< OTG Status register, offset: 0x18
|
|
RESERVED_6 : array[0..2] of byte;
|
|
OTGCTL : byte; // *< OTG Control register, offset: 0x1C
|
|
RESERVED_7 : array[0..98] of byte;
|
|
ISTAT : byte; // *< Interrupt Status register, offset: 0x80
|
|
RESERVED_8 : array[0..2] of byte;
|
|
INTEN : byte; // *< Interrupt Enable register, offset: 0x84
|
|
RESERVED_9 : array[0..2] of byte;
|
|
ERRSTAT : byte; // *< Error Interrupt Status register, offset: 0x88
|
|
RESERVED_10 : array[0..2] of byte;
|
|
ERREN : byte; // *< Error Interrupt Enable register, offset: 0x8C
|
|
RESERVED_11 : array[0..2] of byte;
|
|
STAT : byte; // *< Status register, offset: 0x90
|
|
RESERVED_12 : array[0..2] of byte;
|
|
CTL : byte; // *< Control register, offset: 0x94
|
|
RESERVED_13 : array[0..2] of byte;
|
|
ADDR : byte; // *< Address register, offset: 0x98
|
|
RESERVED_14 : array[0..2] of byte;
|
|
BDTPAGE1 : byte; // *< BDT Page register 1, offset: 0x9C
|
|
RESERVED_15 : array[0..2] of byte;
|
|
FRMNUML : byte; // *< Frame Number register Low, offset: 0xA0
|
|
RESERVED_16 : array[0..2] of byte;
|
|
FRMNUMH : byte; // *< Frame Number register High, offset: 0xA4
|
|
RESERVED_17 : array[0..2] of byte;
|
|
TOKEN : byte; // *< Token register, offset: 0xA8
|
|
RESERVED_18 : array[0..2] of byte;
|
|
SOFTHLD : byte; // *< SOF Threshold register, offset: 0xAC
|
|
RESERVED_19 : array[0..2] of byte;
|
|
BDTPAGE2 : byte; // *< BDT Page Register 2, offset: 0xB0
|
|
RESERVED_20 : array[0..2] of byte;
|
|
BDTPAGE3 : byte; // *< BDT Page Register 3, offset: 0xB4
|
|
RESERVED_21 : array[0..10] of byte;
|
|
ENDPOINT : array[0..15] of TUSB_ENDPOINT;
|
|
USBCTRL : byte; // *< USB Control register, offset: 0x100
|
|
RESERVED_22 : array[0..2] of byte;
|
|
OBSERVE : byte; // *< USB OTG Observe register, offset: 0x104
|
|
RESERVED_23 : array[0..2] of byte;
|
|
CONTROL : byte; // *< USB OTG Control register, offset: 0x108
|
|
RESERVED_24 : array[0..2] of byte;
|
|
USBTRC0 : byte; // *< USB Transceiver Control register 0, offset: 0x10C
|
|
RESERVED_25 : array[0..6] of byte;
|
|
USBFRMADJUST : byte; // *< Frame Adjust Register, offset: 0x114
|
|
RESERVED_26 : array[0..42] of byte;
|
|
CLK_RECOVER_CTRL : byte; // *< USB Clock recovery control, offset: 0x140
|
|
RESERVED_27 : array[0..2] of byte;
|
|
CLK_RECOVER_IRC_EN : byte; // *< IRC48M oscillator enable register, offset: 0x144
|
|
RESERVED_28 : array[0..22] of byte;
|
|
CLK_RECOVER_INT_STATUS : byte; // *< Clock recovery separated interrupt status, offset: 0x15C
|
|
end;
|
|
|
|
const
|
|
USB0_BASE = $40072000;
|
|
|
|
var
|
|
USB0 : TUSB_Registers absolute USB0_BASE;
|
|
|
|
type
|
|
TVREF_Registers = record
|
|
TRM : byte; // *< VREF Trim Register, offset: 0x0
|
|
SC : byte; // *< VREF Status and Control Register, offset: 0x1
|
|
end;
|
|
|
|
const
|
|
VREF_BASE = $40074000;
|
|
|
|
var
|
|
VREF : TVREF_Registers absolute VREF_BASE;
|
|
|
|
type
|
|
TWDOG_Registers = record
|
|
STCTRLH : word; // *< Watchdog Status and Control Register High, offset: 0x0
|
|
STCTRLL : word; // *< Watchdog Status and Control Register Low, offset: 0x2
|
|
TOVALH : word; // *< Watchdog Time-out Value Register High, offset: 0x4
|
|
TOVALL : word; // *< Watchdog Time-out Value Register Low, offset: 0x6
|
|
WINH : word; // *< Watchdog Window Register High, offset: 0x8
|
|
WINL : word; // *< Watchdog Window Register Low, offset: 0xA
|
|
REFRESH : word; // *< Watchdog Refresh register, offset: 0xC
|
|
UNLOCK : word; // *< Watchdog Unlock register, offset: 0xE
|
|
TMROUTH : word; // *< Watchdog Timer Output Register High, offset: 0x10
|
|
TMROUTL : word; // *< Watchdog Timer Output Register Low, offset: 0x12
|
|
RSTCNT : word; // *< Watchdog Reset Count register, offset: 0x14
|
|
PRESC : word; // *< Watchdog Prescaler register, offset: 0x16
|
|
end;
|
|
|
|
const
|
|
WDOG_BASE = $40052000;
|
|
|
|
var
|
|
WDOG : TWDOG_Registers absolute WDOG_BASE;
|
|
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implementation
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procedure NonMaskableInt_interrupt; external name 'NonMaskableInt_interrupt';
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procedure HardFault_interrupt; external name 'HardFault_interrupt';
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procedure MemoryManagement_interrupt; external name 'MemoryManagement_interrupt';
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procedure BusFault_interrupt; external name 'BusFault_interrupt';
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procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
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procedure SVCall_interrupt; external name 'SVCall_interrupt';
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procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
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procedure PendSV_interrupt; external name 'PendSV_interrupt';
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procedure SysTick_interrupt; external name 'SysTick_interrupt';
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procedure DMA0_interrupt; external name 'DMA0_interrupt';
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procedure DMA1_interrupt; external name 'DMA1_interrupt';
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procedure DMA2_interrupt; external name 'DMA2_interrupt';
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procedure DMA3_interrupt; external name 'DMA3_interrupt';
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procedure DMA4_interrupt; external name 'DMA4_interrupt';
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procedure DMA5_interrupt; external name 'DMA5_interrupt';
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procedure DMA6_interrupt; external name 'DMA6_interrupt';
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procedure DMA7_interrupt; external name 'DMA7_interrupt';
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procedure DMA8_interrupt; external name 'DMA8_interrupt';
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procedure DMA9_interrupt; external name 'DMA9_interrupt';
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procedure DMA10_interrupt; external name 'DMA10_interrupt';
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procedure DMA11_interrupt; external name 'DMA11_interrupt';
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procedure DMA12_interrupt; external name 'DMA12_interrupt';
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procedure DMA13_interrupt; external name 'DMA13_interrupt';
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procedure DMA14_interrupt; external name 'DMA14_interrupt';
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procedure DMA15_interrupt; external name 'DMA15_interrupt';
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procedure DMA_Error_interrupt; external name 'DMA_Error_interrupt';
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procedure MCM_interrupt; external name 'MCM_interrupt';
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procedure FTF_interrupt; external name 'FTF_interrupt';
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procedure Read_Collision_interrupt; external name 'Read_Collision_interrupt';
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procedure LVD_LVW_interrupt; external name 'LVD_LVW_interrupt';
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procedure LLW_interrupt; external name 'LLW_interrupt';
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procedure Watchdog_interrupt; external name 'Watchdog_interrupt';
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procedure RNG_interrupt; external name 'RNG_interrupt';
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procedure I2C0_interrupt; external name 'I2C0_interrupt';
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procedure I2C1_interrupt; external name 'I2C1_interrupt';
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procedure SPI0_interrupt; external name 'SPI0_interrupt';
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procedure SPI1_interrupt; external name 'SPI1_interrupt';
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procedure I2S0_Tx_interrupt; external name 'I2S0_Tx_interrupt';
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procedure I2S0_Rx_interrupt; external name 'I2S0_Rx_interrupt';
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procedure LPUART0_interrupt; external name 'LPUART0_interrupt';
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procedure UART0_RX_TX_interrupt; external name 'UART0_RX_TX_interrupt';
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procedure UART0_ERR_interrupt; external name 'UART0_ERR_interrupt';
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procedure UART1_RX_TX_interrupt; external name 'UART1_RX_TX_interrupt';
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procedure UART1_ERR_interrupt; external name 'UART1_ERR_interrupt';
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procedure UART2_RX_TX_interrupt; external name 'UART2_RX_TX_interrupt';
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procedure UART2_ERR_interrupt; external name 'UART2_ERR_interrupt';
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procedure RESERVED53_interrupt; external name 'RESERVED53_interrupt';
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procedure RESERVED54_interrupt; external name 'RESERVED54_interrupt';
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procedure ADC0_interrupt; external name 'ADC0_interrupt';
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procedure CMP0_interrupt; external name 'CMP0_interrupt';
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procedure CMP1_interrupt; external name 'CMP1_interrupt';
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procedure FTM0_interrupt; external name 'FTM0_interrupt';
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procedure FTM1_interrupt; external name 'FTM1_interrupt';
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procedure FTM2_interrupt; external name 'FTM2_interrupt';
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procedure RESERVED61_interrupt; external name 'RESERVED61_interrupt';
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procedure RTC_interrupt; external name 'RTC_interrupt';
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procedure RTC_Seconds_interrupt; external name 'RTC_Seconds_interrupt';
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procedure PIT0_interrupt; external name 'PIT0_interrupt';
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procedure PIT1_interrupt; external name 'PIT1_interrupt';
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procedure PIT2_interrupt; external name 'PIT2_interrupt';
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procedure PIT3_interrupt; external name 'PIT3_interrupt';
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procedure PDB0_interrupt; external name 'PDB0_interrupt';
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procedure USB0_interrupt; external name 'USB0_interrupt';
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procedure RESERVED70_interrupt; external name 'RESERVED70_interrupt';
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procedure RESERVED71_interrupt; external name 'RESERVED71_interrupt';
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procedure DAC0_interrupt; external name 'DAC0_interrupt';
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procedure MCG_interrupt; external name 'MCG_interrupt';
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procedure LPTimer_interrupt; external name 'LPTimer_interrupt';
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procedure PORTA_interrupt; external name 'PORTA_interrupt';
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procedure PORTB_interrupt; external name 'PORTB_interrupt';
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procedure PORTC_interrupt; external name 'PORTC_interrupt';
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procedure PORTD_interrupt; external name 'PORTD_interrupt';
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procedure PORTE_interrupt; external name 'PORTE_interrupt';
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procedure SWI_interrupt; external name 'SWI_interrupt';
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procedure RESERVED81_interrupt; external name 'RESERVED81_interrupt';
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procedure RESERVED82_interrupt; external name 'RESERVED82_interrupt';
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procedure RESERVED83_interrupt; external name 'RESERVED83_interrupt';
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procedure RESERVED84_interrupt; external name 'RESERVED84_interrupt';
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procedure RESERVED85_interrupt; external name 'RESERVED85_interrupt';
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procedure RESERVED86_interrupt; external name 'RESERVED86_interrupt';
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procedure FTM3_interrupt; external name 'FTM3_interrupt';
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procedure DAC1_interrupt; external name 'DAC1_interrupt';
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procedure ADC1_interrupt; external name 'ADC1_interrupt';
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procedure RESERVED90_interrupt; external name 'RESERVED90_interrupt';
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procedure RESERVED91_interrupt; external name 'RESERVED91_interrupt';
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procedure RESERVED92_interrupt; external name 'RESERVED92_interrupt';
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procedure RESERVED93_interrupt; external name 'RESERVED93_interrupt';
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procedure RESERVED94_interrupt; external name 'RESERVED94_interrupt';
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procedure RESERVED95_interrupt; external name 'RESERVED95_interrupt';
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procedure RESERVED96_interrupt; external name 'RESERVED96_interrupt';
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procedure RESERVED97_interrupt; external name 'RESERVED97_interrupt';
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procedure RESERVED98_interrupt; external name 'RESERVED98_interrupt';
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procedure RESERVED99_interrupt; external name 'RESERVED99_interrupt';
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procedure RESERVED100_interrupt; external name 'RESERVED100_interrupt';
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procedure RESERVED101_interrupt; external name 'RESERVED101_interrupt';
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{$i cortexm4f_start.inc}
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procedure FlashConfiguration; assembler; nostackframe;
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label flash_conf;
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asm
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.section ".flash_config.flash_conf"
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flash_conf:
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.byte 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFF
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.text
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end;
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procedure LowLevelStartup; assembler; nostackframe; [public, alias: '_LOWLEVELSTART'];
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asm
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// Unlock watchdog
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ldr r0, .LWDOG_BASE
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movw r1, #0xc520 //50464
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strh r1, [r0, #0xE]
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movw r1, #0xd928 //55592
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strh r1, [r0, #0xE]
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nop
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nop
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// Disable watchdog for now
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movs r1, #0x1d2
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strh r1, [r0, #0]
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b Startup
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.LWDOG_BASE:
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.long 0x40052000
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end;
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procedure Vectors; assembler; nostackframe;
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label interrupt_vectors;
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asm
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.section ".init.interrupt_vectors"
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interrupt_vectors:
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.long _stack_top
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.long LowLevelStartup
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.long NonMaskableInt_interrupt
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.long HardFault_interrupt
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.long MemoryManagement_interrupt
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.long BusFault_interrupt
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.long UsageFault_interrupt
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.long 0
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.long 0
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.long 0
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.long 0
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.long SVCall_interrupt
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.long DebugMonitor_interrupt
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.long 0
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.long PendSV_interrupt
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.long SysTick_interrupt
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.long DMA0_interrupt
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.long DMA1_interrupt
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.long DMA2_interrupt
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.long DMA3_interrupt
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.long DMA4_interrupt
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.long DMA5_interrupt
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.long DMA6_interrupt
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.long DMA7_interrupt
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.long DMA8_interrupt
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.long DMA9_interrupt
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.long DMA10_interrupt
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.long DMA11_interrupt
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.long DMA12_interrupt
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.long DMA13_interrupt
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.long DMA14_interrupt
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.long DMA15_interrupt
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.long DMA_Error_interrupt
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.long MCM_interrupt
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.long FTF_interrupt
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.long Read_Collision_interrupt
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.long LVD_LVW_interrupt
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.long LLW_interrupt
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.long Watchdog_interrupt
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.long RNG_interrupt
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.long I2C0_interrupt
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.long I2C1_interrupt
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.long SPI0_interrupt
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.long SPI1_interrupt
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.long I2S0_Tx_interrupt
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.long I2S0_Rx_interrupt
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.long LPUART0_interrupt
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.long UART0_RX_TX_interrupt
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.long UART0_ERR_interrupt
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.long UART1_RX_TX_interrupt
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.long UART1_ERR_interrupt
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.long UART2_RX_TX_interrupt
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.long UART2_ERR_interrupt
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.long RESERVED53_interrupt
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.long RESERVED54_interrupt
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.long ADC0_interrupt
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.long CMP0_interrupt
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.long CMP1_interrupt
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.long FTM0_interrupt
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.long FTM1_interrupt
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.long FTM2_interrupt
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.long RESERVED61_interrupt
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.long RTC_interrupt
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.long RTC_Seconds_interrupt
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.long PIT0_interrupt
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.long PIT1_interrupt
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.long PIT2_interrupt
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.long PIT3_interrupt
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.long PDB0_interrupt
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.long USB0_interrupt
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.long RESERVED70_interrupt
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.long RESERVED71_interrupt
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.long DAC0_interrupt
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.long MCG_interrupt
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.long LPTimer_interrupt
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.long PORTA_interrupt
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.long PORTB_interrupt
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.long PORTC_interrupt
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.long PORTD_interrupt
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.long PORTE_interrupt
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.long SWI_interrupt
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.long RESERVED81_interrupt
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.long RESERVED82_interrupt
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.long RESERVED83_interrupt
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.long RESERVED84_interrupt
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.long RESERVED85_interrupt
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.long RESERVED86_interrupt
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.long FTM3_interrupt
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.long DAC1_interrupt
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.long ADC1_interrupt
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.long RESERVED90_interrupt
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.long RESERVED91_interrupt
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.long RESERVED92_interrupt
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.long RESERVED93_interrupt
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.long RESERVED94_interrupt
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.long RESERVED95_interrupt
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.long RESERVED96_interrupt
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.long RESERVED97_interrupt
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.long RESERVED98_interrupt
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.long RESERVED99_interrupt
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.long RESERVED100_interrupt
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.long RESERVED101_interrupt
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.weak NonMaskableInt_interrupt
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.weak HardFault_interrupt
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.weak MemoryManagement_interrupt
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.weak BusFault_interrupt
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.weak UsageFault_interrupt
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.weak SVCall_interrupt
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.weak DebugMonitor_interrupt
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.weak PendSV_interrupt
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.weak SysTick_interrupt
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.weak DMA0_interrupt
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.weak DMA1_interrupt
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.weak DMA2_interrupt
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.weak DMA3_interrupt
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.weak DMA4_interrupt
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.weak DMA5_interrupt
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.weak DMA6_interrupt
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.weak DMA7_interrupt
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.weak DMA8_interrupt
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.weak DMA9_interrupt
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.weak DMA10_interrupt
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.weak DMA11_interrupt
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.weak DMA12_interrupt
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.weak DMA13_interrupt
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.weak DMA14_interrupt
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.weak DMA15_interrupt
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.weak DMA_Error_interrupt
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.weak MCM_interrupt
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.weak FTF_interrupt
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.weak Read_Collision_interrupt
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.weak LVD_LVW_interrupt
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.weak LLW_interrupt
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.weak Watchdog_interrupt
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.weak RNG_interrupt
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.weak I2C0_interrupt
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.weak I2C1_interrupt
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.weak SPI0_interrupt
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.weak SPI1_interrupt
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.weak I2S0_Tx_interrupt
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.weak I2S0_Rx_interrupt
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.weak LPUART0_interrupt
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.weak UART0_RX_TX_interrupt
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.weak UART0_ERR_interrupt
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.weak UART1_RX_TX_interrupt
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.weak UART1_ERR_interrupt
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.weak UART2_RX_TX_interrupt
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.weak UART2_ERR_interrupt
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.weak RESERVED53_interrupt
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.weak RESERVED54_interrupt
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.weak ADC0_interrupt
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.weak CMP0_interrupt
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.weak CMP1_interrupt
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.weak FTM0_interrupt
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.weak FTM1_interrupt
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.weak FTM2_interrupt
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.weak RESERVED61_interrupt
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.weak RTC_interrupt
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.weak RTC_Seconds_interrupt
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.weak PIT0_interrupt
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.weak PIT1_interrupt
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.weak PIT2_interrupt
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.weak PIT3_interrupt
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.weak PDB0_interrupt
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.weak USB0_interrupt
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.weak RESERVED70_interrupt
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.weak RESERVED71_interrupt
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.weak DAC0_interrupt
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.weak MCG_interrupt
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.weak LPTimer_interrupt
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.weak PORTA_interrupt
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.weak PORTB_interrupt
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.weak PORTC_interrupt
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.weak PORTD_interrupt
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.weak PORTE_interrupt
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.weak SWI_interrupt
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.weak RESERVED81_interrupt
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.weak RESERVED82_interrupt
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.weak RESERVED83_interrupt
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.weak RESERVED84_interrupt
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.weak RESERVED85_interrupt
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.weak RESERVED86_interrupt
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.weak FTM3_interrupt
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.weak DAC1_interrupt
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.weak ADC1_interrupt
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.weak RESERVED90_interrupt
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.weak RESERVED91_interrupt
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.weak RESERVED92_interrupt
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.weak RESERVED93_interrupt
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.weak RESERVED94_interrupt
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.weak RESERVED95_interrupt
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.weak RESERVED96_interrupt
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.weak RESERVED97_interrupt
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.weak RESERVED98_interrupt
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.weak RESERVED99_interrupt
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.weak RESERVED100_interrupt
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.weak RESERVED101_interrupt
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.set NonMaskableInt_interrupt, HaltProc
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.set HardFault_interrupt, HaltProc
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.set MemoryManagement_interrupt, HaltProc
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.set BusFault_interrupt, HaltProc
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.set UsageFault_interrupt, HaltProc
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.set SVCall_interrupt, HaltProc
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.set DebugMonitor_interrupt, HaltProc
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.set PendSV_interrupt, HaltProc
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.set SysTick_interrupt, HaltProc
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.set DMA0_interrupt, HaltProc
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.set DMA1_interrupt, HaltProc
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.set DMA2_interrupt, HaltProc
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.set DMA3_interrupt, HaltProc
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.set DMA4_interrupt, HaltProc
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.set DMA5_interrupt, HaltProc
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.set DMA6_interrupt, HaltProc
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.set DMA7_interrupt, HaltProc
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.set DMA8_interrupt, HaltProc
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.set DMA9_interrupt, HaltProc
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.set DMA10_interrupt, HaltProc
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.set DMA11_interrupt, HaltProc
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.set DMA12_interrupt, HaltProc
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.set DMA13_interrupt, HaltProc
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.set DMA14_interrupt, HaltProc
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.set DMA15_interrupt, HaltProc
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.set DMA_Error_interrupt, HaltProc
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.set MCM_interrupt, HaltProc
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.set FTF_interrupt, HaltProc
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.set Read_Collision_interrupt, HaltProc
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.set LVD_LVW_interrupt, HaltProc
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.set LLW_interrupt, HaltProc
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.set Watchdog_interrupt, HaltProc
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.set RNG_interrupt, HaltProc
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.set I2C0_interrupt, HaltProc
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.set I2C1_interrupt, HaltProc
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.set SPI0_interrupt, HaltProc
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.set SPI1_interrupt, HaltProc
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.set I2S0_Tx_interrupt, HaltProc
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.set I2S0_Rx_interrupt, HaltProc
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.set LPUART0_interrupt, HaltProc
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.set UART0_RX_TX_interrupt, HaltProc
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.set UART0_ERR_interrupt, HaltProc
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.set UART1_RX_TX_interrupt, HaltProc
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.set UART1_ERR_interrupt, HaltProc
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.set UART2_RX_TX_interrupt, HaltProc
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.set UART2_ERR_interrupt, HaltProc
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.set RESERVED53_interrupt, HaltProc
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.set RESERVED54_interrupt, HaltProc
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.set ADC0_interrupt, HaltProc
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.set CMP0_interrupt, HaltProc
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.set CMP1_interrupt, HaltProc
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.set FTM0_interrupt, HaltProc
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.set FTM1_interrupt, HaltProc
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.set FTM2_interrupt, HaltProc
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.set RESERVED61_interrupt, HaltProc
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.set RTC_interrupt, HaltProc
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.set RTC_Seconds_interrupt, HaltProc
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.set PIT0_interrupt, HaltProc
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.set PIT1_interrupt, HaltProc
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.set PIT2_interrupt, HaltProc
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.set PIT3_interrupt, HaltProc
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.set PDB0_interrupt, HaltProc
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.set USB0_interrupt, HaltProc
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.set RESERVED70_interrupt, HaltProc
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.set RESERVED71_interrupt, HaltProc
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.set DAC0_interrupt, HaltProc
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.set MCG_interrupt, HaltProc
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.set LPTimer_interrupt, HaltProc
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.set PORTA_interrupt, HaltProc
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.set PORTB_interrupt, HaltProc
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.set PORTC_interrupt, HaltProc
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.set PORTD_interrupt, HaltProc
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.set PORTE_interrupt, HaltProc
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.set SWI_interrupt, HaltProc
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.set RESERVED81_interrupt, HaltProc
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.set RESERVED82_interrupt, HaltProc
|
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.set RESERVED83_interrupt, HaltProc
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|
.set RESERVED84_interrupt, HaltProc
|
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.set RESERVED85_interrupt, HaltProc
|
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.set RESERVED86_interrupt, HaltProc
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.set FTM3_interrupt, HaltProc
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.set DAC1_interrupt, HaltProc
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.set ADC1_interrupt, HaltProc
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.set RESERVED90_interrupt, HaltProc
|
|
.set RESERVED91_interrupt, HaltProc
|
|
.set RESERVED92_interrupt, HaltProc
|
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.set RESERVED93_interrupt, HaltProc
|
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.set RESERVED94_interrupt, HaltProc
|
|
.set RESERVED95_interrupt, HaltProc
|
|
.set RESERVED96_interrupt, HaltProc
|
|
.set RESERVED97_interrupt, HaltProc
|
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.set RESERVED98_interrupt, HaltProc
|
|
.set RESERVED99_interrupt, HaltProc
|
|
.set RESERVED100_interrupt, HaltProc
|
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.set RESERVED101_interrupt, HaltProc
|
|
.text
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end;
|
|
end.
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