mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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7dac620e2d
- bxCAN controller only has 2 RX mailboxes. The registers behind were misplaced. Refer to RM0008 section 24.9.3 and 24.9.4
720 lines
20 KiB
ObjectPascal
720 lines
20 KiB
ObjectPascal
{
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Register definitions and utility code for STM32F10x - Low Density
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Created by Jeppe Johansen 2012 - jeppe@j-software.dk
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}
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{$IFNDEF FPC_DOTTEDUNITS}
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unit stm32f10x_ld;
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{$ENDIF FPC_DOTTEDUNITS}
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{$goto on}
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{$define stm32f10x_ld}
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interface
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type
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TBitvector32 = bitpacked array[0..31] of 0..1;
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{$PACKRECORDS 2}
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const
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PeripheralBase = $40000000;
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FSMCBase = $60000000;
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APB1Base = PeripheralBase;
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APB2Base = PeripheralBase+$10000;
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AHBBase = PeripheralBase+$20000;
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{ FSMC }
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FSMCBank1NOR1 = FSMCBase+$00000000;
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FSMCBank1NOR2 = FSMCBase+$04000000;
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FSMCBank1NOR3 = FSMCBase+$08000000;
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FSMCBank1NOR4 = FSMCBase+$0C000000;
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FSMCBank1PSRAM1 = FSMCBase+$00000000;
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FSMCBank1PSRAM2 = FSMCBase+$04000000;
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FSMCBank1PSRAM3 = FSMCBase+$08000000;
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FSMCBank1PSRAM4 = FSMCBase+$0C000000;
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FSMCBank2NAND1 = FSMCBase+$10000000;
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FSMCBank3NAND2 = FSMCBase+$20000000;
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FSMCBank4PCCARD = FSMCBase+$30000000;
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type
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TTimerRegisters = record
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CR1, res1,
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CR2, res2,
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SMCR, res3,
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DIER, res4,
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SR, res5,
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EGR, res,
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CCMR1, res6,
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CCMR2, res7,
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CCER, res8,
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CNT, res9,
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PSC, res10,
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ARR, res11,
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RCR, res12,
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CCR1, res13,
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CCR2, res14,
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CCR3, res15,
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CCR4, res16,
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BDTR, res17,
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DCR, res18,
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DMAR, res19: Word;
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end;
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TRTCRegisters = record
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CRH, res1,
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CRL, res2,
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PRLH, res3,
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PRLL, res4,
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DIVH, res5,
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DIVL, res6,
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CNTH, res7,
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CNTL, res8,
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ALRH, res9,
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ALRL, res10: Word;
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end;
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TIWDGRegisters = record
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KR, res1,
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PR, res2,
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RLR, res3,
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SR, res4: word;
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end;
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TWWDGRegisters = record
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CR, res2,
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CFR, res3,
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SR, res4: word;
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end;
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TSPIRegisters = record
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CR1, res1,
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CR2, res2,
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SR, res3,
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DR, res4,
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CRCPR, res5,
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RXCRCR, res6,
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TXCRCR, res7,
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I2SCFGR, res8,
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I2SPR, res9: Word;
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end;
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TUSARTRegisters = record
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SR, res1,
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DR, res2,
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BRR, res3,
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CR1, res4,
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CR2, res5,
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CR3, res6,
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GTPR, res7: Word;
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end;
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TI2CRegisters = record
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CR1, res1,
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CR2, res2,
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OAR1, res3,
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OAR2, res4,
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DR, res5,
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SR1, res6,
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SR2, res7,
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CCR, res8: word;
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TRISE: byte;
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end;
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TUSBRegisters = record
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EPR: array[0..7] of longword;
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res: array[0..7] of longword;
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CNTR, res1,
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ISTR, res2,
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FNR, res3: Word;
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DADDR: byte; res4: word; res5: byte;
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BTABLE: Word;
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end;
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TUSBMem = packed array[0..511] of byte;
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TCANMailbox = record
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IR,
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DTR,
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DLR,
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DHR: longword;
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end;
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TCANRegisters = record
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MCR,
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MSR,
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TSR,
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RF0R,
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RF1R,
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IER,
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ESR,
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BTR: longword;
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res5: array[$020..$17F] of byte;
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TX: array[0..2] of TCANMailbox;
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RX: array[0..1] of TCANMailbox;
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res6: array[$1D0..$1FF] of byte;
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FMR,
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FM1R,
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res9: longword;
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FS1R, res10: word;
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res11: longword;
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FFA1R, res12: word;
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res13: longword;
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FA1R, res14: word;
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res15: array[$220..$23F] of byte;
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FOR1,
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FOR2: longword;
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FB: array[1..13] of array[1..2] of longword;
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end;
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TBKPRegisters = record
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DR: array[1..10] of record data, res: word; end;
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RTCCR,
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CR,
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CSR,
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res1,res2: longword;
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DR2: array[11..42] of record data, res: word; end;
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end;
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TPwrRegisters = record
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CR, res: word;
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CSR: Word;
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end;
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TDACRegisters = record
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CR,
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SWTRIGR: longword;
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DHR12R1, res2,
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DHR12L1, res3,
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DHR8R1, res4,
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DHR12R2, res5,
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DHR12L2, res6,
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DHR8R2, res7: word;
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DHR12RD,
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DHR12LD: longword;
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DHR8RD, res8,
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DOR1, res9,
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DOR2, res10: Word;
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end;
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TAFIORegisters = record
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EVCR,
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MAPR: longword;
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EXTICR: array[0..3] of longword;
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end;
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TEXTIRegisters = record
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IMR,
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EMR,
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RTSR,
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FTSR,
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SWIER,
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PR: longword;
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end;
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TPortRegisters = record
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CRL,
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CRH,
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IDR,
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ODR,
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BSRR,
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BRR,
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LCKR: longword;
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end;
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TADCRegisters = record
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SR,
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CR1,
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CR2,
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SMPR1,
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SMPR2: longword;
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JOFR1, res2,
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JOFR2, res3,
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JOFR3, res4,
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JOFR4, res5,
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HTR, res6,
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LTR, res7: word;
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SQR1,
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SQR2,
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SQR3,
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JSQR: longword;
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JDR1, res8,
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JDR2, res9,
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JDR3, res10,
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JDR4, res11: Word;
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DR: longword;
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end;
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TSDIORegisters = record
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POWER,
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CLKCR,
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ARG: longword;
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CMD, res3,
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RESPCMD, res4: Word;
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RESP1,
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RESP2,
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RESP3,
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RESP4,
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DTIMER,
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DLEN: longword;
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DCTRL, res5: word;
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DCOUNT,
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STA,
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ICR,
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MASK,
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FIFOCNT,
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FIFO: longword;
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end;
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TDMAChannel = record
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CCR, res1,
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CNDTR, res2: word;
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CPAR,
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CMAR,
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res: longword;
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end;
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TDMARegisters = record
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ISR,
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IFCR: longword;
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Channel: array[0..7] of TDMAChannel;
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end;
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TRCCRegisters = record
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CR,
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CFGR,
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CIR,
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APB2RSTR,
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APB1RSTR,
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AHBENR,
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APB2ENR,
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APB1ENR,
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BDCR,
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CSR: longword;
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end;
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TCRCRegisters = record
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DR: longword;
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IDR: byte; res1: word; res2: byte;
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CR: byte;
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end;
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TFlashRegisters = record
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ACR,
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KEYR,
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OPTKEYR,
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SR,
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CR,
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AR,
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res,
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OBR,
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WRPR: longword;
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end;
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{$ALIGN 2}
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var
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{ Timers }
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Timer1: TTimerRegisters absolute (APB2Base+$2C00);
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Timer2: TTimerRegisters absolute (APB1Base+$0000);
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Timer3: TTimerRegisters absolute (APB1Base+$0400);
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Timer4: TTimerRegisters absolute (APB1Base+$0800);
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Timer5: TTimerRegisters absolute (APB1Base+$0C00);
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Timer6: TTimerRegisters absolute (APB1Base+$1000);
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Timer7: TTimerRegisters absolute (APB1Base+$1400);
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Timer8: TTimerRegisters absolute (APB2Base+$3400);
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{ RTC }
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RTC: TRTCRegisters absolute (APB1Base+$2800);
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{ WDG }
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WWDG: TWWDGRegisters absolute (APB1Base+$2C00);
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IWDG: TIWDGRegisters absolute (APB1Base+$3000);
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{ SPI }
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SPI1: TSPIRegisters absolute (APB2Base+$3000);
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SPI2: TSPIRegisters absolute (APB1Base+$3800);
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SPI3: TSPIRegisters absolute (APB1Base+$3C00);
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{ USART/UART }
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USART1: TUSARTRegisters absolute (APB2Base+$3800);
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USART2: TUSARTRegisters absolute (APB1Base+$4400);
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USART3: TUSARTRegisters absolute (APB1Base+$4800);
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UART4: TUSARTRegisters absolute (APB1Base+$4C00);
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UART5: TUSARTRegisters absolute (APB1Base+$5000);
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{ I2C }
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I2C1: TI2CRegisters absolute (APB1Base+$5400);
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I2C2: TI2CRegisters absolute (APB1Base+$5800);
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{ USB }
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USB: TUSBRegisters absolute (APB1Base+$5C00);
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USBMem: TUSBMem absolute (APB1Base+$6000);
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{ CAN }
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CAN: TCANRegisters absolute (APB1Base+$6800);
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{ BKP }
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BKP: TBKPRegisters absolute (APB1Base+$6C00);
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{ PWR }
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PWR: TPwrRegisters absolute (APB1Base+$7000);
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{ DAC }
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DAC: TDACRegisters absolute (APB1Base+$7400);
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{ GPIO }
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AFIO: TAFIORegisters absolute (APB2Base+$0);
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EXTI: TEXTIRegisters absolute (APB2Base+$0400);
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PortA: TPortRegisters absolute (APB2Base+$0800);
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PortB: TPortRegisters absolute (APB2Base+$0C00);
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PortC: TPortRegisters absolute (APB2Base+$1000);
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PortD: TPortRegisters absolute (APB2Base+$1400);
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PortE: TPortRegisters absolute (APB2Base+$1800);
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PortF: TPortRegisters absolute (APB2Base+$1C00);
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PortG: TPortRegisters absolute (APB2Base+$2000);
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{ ADC }
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ADC1: TADCRegisters absolute (APB2Base+$2400);
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ADC2: TADCRegisters absolute (APB2Base+$2800);
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ADC3: TADCRegisters absolute (APB2Base+$3C00);
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{ SDIO }
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SDIO: TSDIORegisters absolute (APB2Base+$8000);
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{ DMA }
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DMA1: TDMARegisters absolute (AHBBase+$0000);
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DMA2: TDMARegisters absolute (AHBBase+$0400);
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{ RCC }
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RCC: TRCCRegisters absolute (AHBBase+$1000);
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{ Flash }
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Flash: TFlashRegisters absolute (AHBBase+$2000);
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{ CRC }
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CRC: TCRCRegisters absolute (AHBBase+$3000);
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implementation
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procedure NMI_interrupt; external name 'NMI_interrupt';
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procedure Hardfault_interrupt; external name 'Hardfault_interrupt';
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procedure MemManage_interrupt; external name 'MemManage_interrupt';
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procedure BusFault_interrupt; external name 'BusFault_interrupt';
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procedure UsageFault_interrupt; external name 'UsageFault_interrupt';
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procedure SWI_interrupt; external name 'SWI_interrupt';
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procedure DebugMonitor_interrupt; external name 'DebugMonitor_interrupt';
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procedure PendingSV_interrupt; external name 'PendingSV_interrupt';
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procedure SysTick_interrupt; external name 'SysTick_interrupt';
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procedure Window_watchdog_interrupt; external name 'Window_watchdog_interrupt';
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procedure PVD_through_EXTI_Line_detection_interrupt; external name 'PVD_through_EXTI_Line_detection_interrupt';
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procedure Tamper_interrupt; external name 'Tamper_interrupt';
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procedure RTC_global_interrupt; external name 'RTC_global_interrupt';
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procedure Flash_global_interrupt; external name 'Flash_global_interrupt';
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procedure RCC_global_interrupt; external name 'RCC_global_interrupt';
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procedure EXTI_Line0_interrupt; external name 'EXTI_Line0_interrupt';
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procedure EXTI_Line1_interrupt; external name 'EXTI_Line1_interrupt';
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procedure EXTI_Line2_interrupt; external name 'EXTI_Line2_interrupt';
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procedure EXTI_Line3_interrupt; external name 'EXTI_Line3_interrupt';
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procedure EXTI_Line4_interrupt; external name 'EXTI_Line4_interrupt';
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procedure DMA1_Channel1_global_interrupt; external name 'DMA1_Channel1_global_interrupt';
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procedure DMA1_Channel2_global_interrupt; external name 'DMA1_Channel2_global_interrupt';
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procedure DMA1_Channel3_global_interrupt; external name 'DMA1_Channel3_global_interrupt';
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procedure DMA1_Channel4_global_interrupt; external name 'DMA1_Channel4_global_interrupt';
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procedure DMA1_Channel5_global_interrupt; external name 'DMA1_Channel5_global_interrupt';
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procedure DMA1_Channel6_global_interrupt; external name 'DMA1_Channel6_global_interrupt';
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procedure DMA1_Channel7_global_interrupt; external name 'DMA1_Channel7_global_interrupt';
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procedure ADC1_and_ADC2_global_interrupt; external name 'ADC1_and_ADC2_global_interrupt';
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procedure USB_High_Priority_or_CAN_TX_interrupts; external name 'USB_High_Priority_or_CAN_TX_interrupts';
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procedure USB_Low_Priority_or_CAN_RX0_interrupts; external name 'USB_Low_Priority_or_CAN_RX0_interrupts';
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procedure CAN_RX1_interrupt; external name 'CAN_RX1_interrupt';
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procedure CAN_SCE_interrupt; external name 'CAN_SCE_interrupt';
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procedure EXTI_Line9_5_interrupts; external name 'EXTI_Line9_5_interrupts';
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procedure TIM1_Break_interrupt; external name 'TIM1_Break_interrupt';
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procedure TIM1_Update_interrupt; external name 'TIM1_Update_interrupt';
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procedure TIM1_Trigger_and_Commutation_interrupts; external name 'TIM1_Trigger_and_Commutation_interrupts';
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procedure TIM1_Capture_Compare_interrupt; external name 'TIM1_Capture_Compare_interrupt';
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procedure TIM2_global_interrupt; external name 'TIM2_global_interrupt';
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procedure TIM3_global_interrupt; external name 'TIM3_global_interrupt';
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procedure TIM4_global_interrupt; external name 'TIM4_global_interrupt';
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procedure I2C1_event_interrupt; external name 'I2C1_event_interrupt';
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procedure I2C1_error_interrupt; external name 'I2C1_error_interrupt';
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procedure I2C2_event_interrupt; external name 'I2C2_event_interrupt';
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procedure I2C2_error_interrupt; external name 'I2C2_error_interrupt';
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procedure SPI1_global_interrupt; external name 'SPI1_global_interrupt';
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procedure SPI2_global_interrupt; external name 'SPI2_global_interrupt';
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procedure USART1_global_interrupt; external name 'USART1_global_interrupt';
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procedure USART2_global_interrupt; external name 'USART2_global_interrupt';
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procedure USART3_global_interrupt; external name 'USART3_global_interrupt';
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procedure EXTI_Line15_10_interrupts; external name 'EXTI_Line15_10_interrupts';
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procedure RTC_alarm_through_EXTI_line_interrupt; external name 'RTC_alarm_through_EXTI_line_interrupt';
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procedure USB_wakeup_from_suspend_through_EXTI_line_interrupt; external name 'USB_wakeup_from_suspend_through_EXTI_line_interrupt';
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procedure TIM8_Break_interrupt; external name 'TIM8_Break_interrupt';
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procedure TIM8_Update_interrupt; external name 'TIM8_Update_interrupt';
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procedure TIM8_Trigger_and_Commutation_interrupts; external name 'TIM8_Trigger_and_Commutation_interrupts';
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procedure TIM8_Capture_Compare_interrupt; external name 'TIM8_Capture_Compare_interrupt';
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procedure ADC3_global_interrupt; external name 'ADC3_global_interrupt';
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procedure FSMC_global_interrupt; external name 'FSMC_global_interrupt';
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procedure SDIO_global_interrupt; external name 'SDIO_global_interrupt';
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procedure TIM5_global_interrupt; external name 'TIM5_global_interrupt';
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procedure SPI3_global_interrupt; external name 'SPI3_global_interrupt';
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procedure UART4_global_interrupt; external name 'UART4_global_interrupt';
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procedure UART5_global_interrupt; external name 'UART5_global_interrupt';
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procedure TIM6_global_interrupt; external name 'TIM6_global_interrupt';
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procedure TIM7_global_interrupt; external name 'TIM7_global_interrupt';
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procedure DMA2_Channel1_global_interrupt; external name 'DMA2_Channel1_global_interrupt';
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procedure DMA2_Channel2_global_interrupt; external name 'DMA2_Channel2_global_interrupt';
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procedure DMA2_Channel3_global_interrupt; external name 'DMA2_Channel3_global_interrupt';
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procedure DMA2_Channel4_and_DMA2_Channel5_global_interrupts; external name 'DMA2_Channel4_and_DMA2_Channel5_global_interrupts';
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{$i cortexm3_start.inc}
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procedure Vectors; assembler; nostackframe;
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label interrupt_vectors;
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asm
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.section ".init.interrupt_vectors"
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interrupt_vectors:
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.long _stack_top
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.long Startup
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.long NMI_interrupt
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.long Hardfault_interrupt
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.long MemManage_interrupt
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.long BusFault_interrupt
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.long UsageFault_interrupt
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.long 0
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.long 0
|
|
.long 0
|
|
.long 0
|
|
.long SWI_interrupt
|
|
.long DebugMonitor_interrupt
|
|
.long 0
|
|
.long PendingSV_interrupt
|
|
.long SysTick_interrupt
|
|
|
|
.long Window_watchdog_interrupt
|
|
.long PVD_through_EXTI_Line_detection_interrupt
|
|
.long Tamper_interrupt
|
|
.long RTC_global_interrupt
|
|
.long Flash_global_interrupt
|
|
.long RCC_global_interrupt
|
|
.long EXTI_Line0_interrupt
|
|
.long EXTI_Line1_interrupt
|
|
.long EXTI_Line2_interrupt
|
|
.long EXTI_Line3_interrupt
|
|
.long EXTI_Line4_interrupt
|
|
.long DMA1_Channel1_global_interrupt
|
|
.long DMA1_Channel2_global_interrupt
|
|
.long DMA1_Channel3_global_interrupt
|
|
.long DMA1_Channel4_global_interrupt
|
|
.long DMA1_Channel5_global_interrupt
|
|
.long DMA1_Channel6_global_interrupt
|
|
.long DMA1_Channel7_global_interrupt
|
|
.long ADC1_and_ADC2_global_interrupt
|
|
.long USB_High_Priority_or_CAN_TX_interrupts
|
|
.long USB_Low_Priority_or_CAN_RX0_interrupts
|
|
.long CAN_RX1_interrupt
|
|
.long CAN_SCE_interrupt
|
|
.long EXTI_Line9_5_interrupts
|
|
.long TIM1_Break_interrupt
|
|
.long TIM1_Update_interrupt
|
|
.long TIM1_Trigger_and_Commutation_interrupts
|
|
.long TIM1_Capture_Compare_interrupt
|
|
.long TIM2_global_interrupt
|
|
.long TIM3_global_interrupt
|
|
.long TIM4_global_interrupt
|
|
.long I2C1_event_interrupt
|
|
.long I2C1_error_interrupt
|
|
.long I2C2_event_interrupt
|
|
.long I2C2_error_interrupt
|
|
.long SPI1_global_interrupt
|
|
.long SPI2_global_interrupt
|
|
.long USART1_global_interrupt
|
|
.long USART2_global_interrupt
|
|
.long USART3_global_interrupt
|
|
.long EXTI_Line15_10_interrupts
|
|
.long RTC_alarm_through_EXTI_line_interrupt
|
|
.long USB_wakeup_from_suspend_through_EXTI_line_interrupt
|
|
.long TIM8_Break_interrupt
|
|
.long TIM8_Update_interrupt
|
|
.long TIM8_Trigger_and_Commutation_interrupts
|
|
.long TIM8_Capture_Compare_interrupt
|
|
.long ADC3_global_interrupt
|
|
.long FSMC_global_interrupt
|
|
.long SDIO_global_interrupt
|
|
.long TIM5_global_interrupt
|
|
.long SPI3_global_interrupt
|
|
.long UART4_global_interrupt
|
|
.long UART5_global_interrupt
|
|
.long TIM6_global_interrupt
|
|
.long TIM7_global_interrupt
|
|
.long DMA2_Channel1_global_interrupt
|
|
.long DMA2_Channel2_global_interrupt
|
|
.long DMA2_Channel3_global_interrupt
|
|
.long DMA2_Channel4_and_DMA2_Channel5_global_interrupts
|
|
|
|
.weak NMI_interrupt
|
|
.weak Hardfault_interrupt
|
|
.weak MemManage_interrupt
|
|
.weak BusFault_interrupt
|
|
.weak UsageFault_interrupt
|
|
.weak SWI_interrupt
|
|
.weak DebugMonitor_interrupt
|
|
.weak PendingSV_interrupt
|
|
.weak SysTick_interrupt
|
|
|
|
.weak Window_watchdog_interrupt
|
|
.weak PVD_through_EXTI_Line_detection_interrupt
|
|
.weak Tamper_interrupt
|
|
.weak RTC_global_interrupt
|
|
.weak Flash_global_interrupt
|
|
.weak RCC_global_interrupt
|
|
.weak EXTI_Line0_interrupt
|
|
.weak EXTI_Line1_interrupt
|
|
.weak EXTI_Line2_interrupt
|
|
.weak EXTI_Line3_interrupt
|
|
.weak EXTI_Line4_interrupt
|
|
.weak DMA1_Channel1_global_interrupt
|
|
.weak DMA1_Channel2_global_interrupt
|
|
.weak DMA1_Channel3_global_interrupt
|
|
.weak DMA1_Channel4_global_interrupt
|
|
.weak DMA1_Channel5_global_interrupt
|
|
.weak DMA1_Channel6_global_interrupt
|
|
.weak DMA1_Channel7_global_interrupt
|
|
.weak ADC1_and_ADC2_global_interrupt
|
|
.weak USB_High_Priority_or_CAN_TX_interrupts
|
|
.weak USB_Low_Priority_or_CAN_RX0_interrupts
|
|
.weak CAN_RX1_interrupt
|
|
.weak CAN_SCE_interrupt
|
|
.weak EXTI_Line9_5_interrupts
|
|
.weak TIM1_Break_interrupt
|
|
.weak TIM1_Update_interrupt
|
|
.weak TIM1_Trigger_and_Commutation_interrupts
|
|
.weak TIM1_Capture_Compare_interrupt
|
|
.weak TIM2_global_interrupt
|
|
.weak TIM3_global_interrupt
|
|
.weak TIM4_global_interrupt
|
|
.weak I2C1_event_interrupt
|
|
.weak I2C1_error_interrupt
|
|
.weak I2C2_event_interrupt
|
|
.weak I2C2_error_interrupt
|
|
.weak SPI1_global_interrupt
|
|
.weak SPI2_global_interrupt
|
|
.weak USART1_global_interrupt
|
|
.weak USART2_global_interrupt
|
|
.weak USART3_global_interrupt
|
|
.weak EXTI_Line15_10_interrupts
|
|
.weak RTC_alarm_through_EXTI_line_interrupt
|
|
.weak USB_wakeup_from_suspend_through_EXTI_line_interrupt
|
|
.weak TIM8_Break_interrupt
|
|
.weak TIM8_Update_interrupt
|
|
.weak TIM8_Trigger_and_Commutation_interrupts
|
|
.weak TIM8_Capture_Compare_interrupt
|
|
.weak ADC3_global_interrupt
|
|
.weak FSMC_global_interrupt
|
|
.weak SDIO_global_interrupt
|
|
.weak TIM5_global_interrupt
|
|
.weak SPI3_global_interrupt
|
|
.weak UART4_global_interrupt
|
|
.weak UART5_global_interrupt
|
|
.weak TIM6_global_interrupt
|
|
.weak TIM7_global_interrupt
|
|
.weak DMA2_Channel1_global_interrupt
|
|
.weak DMA2_Channel2_global_interrupt
|
|
.weak DMA2_Channel3_global_interrupt
|
|
.weak DMA2_Channel4_and_DMA2_Channel5_global_interrupts
|
|
|
|
|
|
.set NMI_interrupt, HaltProc
|
|
.set Hardfault_interrupt, HaltProc
|
|
.set MemManage_interrupt, HaltProc
|
|
.set BusFault_interrupt, HaltProc
|
|
.set UsageFault_interrupt, HaltProc
|
|
.set SWI_interrupt, HaltProc
|
|
.set DebugMonitor_interrupt, HaltProc
|
|
.set PendingSV_interrupt, HaltProc
|
|
.set SysTick_interrupt, HaltProc
|
|
|
|
.set Window_watchdog_interrupt, HaltProc
|
|
.set PVD_through_EXTI_Line_detection_interrupt, HaltProc
|
|
.set Tamper_interrupt, HaltProc
|
|
.set RTC_global_interrupt, HaltProc
|
|
.set Flash_global_interrupt, HaltProc
|
|
.set RCC_global_interrupt, HaltProc
|
|
.set EXTI_Line0_interrupt, HaltProc
|
|
.set EXTI_Line1_interrupt, HaltProc
|
|
.set EXTI_Line2_interrupt, HaltProc
|
|
.set EXTI_Line3_interrupt, HaltProc
|
|
.set EXTI_Line4_interrupt, HaltProc
|
|
.set DMA1_Channel1_global_interrupt, HaltProc
|
|
.set DMA1_Channel2_global_interrupt, HaltProc
|
|
.set DMA1_Channel3_global_interrupt, HaltProc
|
|
.set DMA1_Channel4_global_interrupt, HaltProc
|
|
.set DMA1_Channel5_global_interrupt, HaltProc
|
|
.set DMA1_Channel6_global_interrupt, HaltProc
|
|
.set DMA1_Channel7_global_interrupt, HaltProc
|
|
.set ADC1_and_ADC2_global_interrupt, HaltProc
|
|
.set USB_High_Priority_or_CAN_TX_interrupts, HaltProc
|
|
.set USB_Low_Priority_or_CAN_RX0_interrupts, HaltProc
|
|
.set CAN_RX1_interrupt, HaltProc
|
|
.set CAN_SCE_interrupt, HaltProc
|
|
.set EXTI_Line9_5_interrupts, HaltProc
|
|
.set TIM1_Break_interrupt, HaltProc
|
|
.set TIM1_Update_interrupt, HaltProc
|
|
.set TIM1_Trigger_and_Commutation_interrupts, HaltProc
|
|
.set TIM1_Capture_Compare_interrupt, HaltProc
|
|
.set TIM2_global_interrupt, HaltProc
|
|
.set TIM3_global_interrupt, HaltProc
|
|
.set TIM4_global_interrupt, HaltProc
|
|
.set I2C1_event_interrupt, HaltProc
|
|
.set I2C1_error_interrupt, HaltProc
|
|
.set I2C2_event_interrupt, HaltProc
|
|
.set I2C2_error_interrupt, HaltProc
|
|
.set SPI1_global_interrupt, HaltProc
|
|
.set SPI2_global_interrupt, HaltProc
|
|
.set USART1_global_interrupt, HaltProc
|
|
.set USART2_global_interrupt, HaltProc
|
|
.set USART3_global_interrupt, HaltProc
|
|
.set EXTI_Line15_10_interrupts, HaltProc
|
|
.set RTC_alarm_through_EXTI_line_interrupt, HaltProc
|
|
.set USB_wakeup_from_suspend_through_EXTI_line_interrupt, HaltProc
|
|
.set TIM8_Break_interrupt, HaltProc
|
|
.set TIM8_Update_interrupt, HaltProc
|
|
.set TIM8_Trigger_and_Commutation_interrupts, HaltProc
|
|
.set TIM8_Capture_Compare_interrupt, HaltProc
|
|
.set ADC3_global_interrupt, HaltProc
|
|
.set FSMC_global_interrupt, HaltProc
|
|
.set SDIO_global_interrupt, HaltProc
|
|
.set TIM5_global_interrupt, HaltProc
|
|
.set SPI3_global_interrupt, HaltProc
|
|
.set UART4_global_interrupt, HaltProc
|
|
.set UART5_global_interrupt, HaltProc
|
|
.set TIM6_global_interrupt, HaltProc
|
|
.set TIM7_global_interrupt, HaltProc
|
|
.set DMA2_Channel1_global_interrupt, HaltProc
|
|
.set DMA2_Channel2_global_interrupt, HaltProc
|
|
.set DMA2_Channel3_global_interrupt, HaltProc
|
|
.set DMA2_Channel4_and_DMA2_Channel5_global_interrupts, HaltProc
|
|
|
|
.text
|
|
end;
|
|
|
|
end.
|