mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 19:28:13 +02:00
645 lines
26 KiB
ObjectPascal
645 lines
26 KiB
ObjectPascal
unit ATmega32C1;
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interface
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var
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// PORTB
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PORTB : byte absolute $00+$25; // Port B Data Register
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DDRB : byte absolute $00+$24; // Port B Data Direction Register
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PINB : byte absolute $00+$23; // Port B Input Pins
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// PORTC
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PORTC : byte absolute $00+$28; // Port C Data Register
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DDRC : byte absolute $00+$27; // Port C Data Direction Register
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PINC : byte absolute $00+$26; // Port C Input Pins
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// PORTD
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PORTD : byte absolute $00+$2B; // Port D Data Register
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DDRD : byte absolute $00+$2A; // Port D Data Direction Register
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PIND : byte absolute $00+$29; // Port D Input Pins
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// CAN
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CANGCON : byte absolute $00+$D8; // CAN General Control Register
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CANGSTA : byte absolute $00+$D9; // CAN General Status Register
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CANGIT : byte absolute $00+$DA; // CAN General Interrupt Register Flags
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CANGIE : byte absolute $00+$DB; // CAN General Interrupt Enable Register
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CANEN2 : byte absolute $00+$DC; // Enable MOb Register 2
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CANEN1 : byte absolute $00+$DD; // Enable MOb Register 1(empty)
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CANIE2 : byte absolute $00+$DE; // Enable Interrupt MOb Register 2
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CANIE1 : byte absolute $00+$DF; // Enable Interrupt MOb Register 1 (empty)
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CANSIT2 : byte absolute $00+$E0; // CAN Status Interrupt MOb Register 2
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CANSIT1 : byte absolute $00+$E1; // CAN Status Interrupt MOb Register 1 (empty)
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CANBT1 : byte absolute $00+$E2; // CAN Bit Timing Register 1
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CANBT2 : byte absolute $00+$E3; // CAN Bit Timing Register 2
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CANBT3 : byte absolute $00+$E4; // CAN Bit Timing Register 3
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CANTCON : byte absolute $00+$E5; // Timer Control Register
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CANTIML : byte absolute $00+$E6; // Timer Register Low
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CANTIMH : byte absolute $00+$E7; // Timer Register High
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CANTTCL : byte absolute $00+$E8; // TTC Timer Register Low
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CANTTCH : byte absolute $00+$E9; // TTC Timer Register High
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CANTEC : byte absolute $00+$EA; // Transmit Error Counter Register
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CANREC : byte absolute $00+$EB; // Receive Error Counter Register
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CANHPMOB : byte absolute $00+$EC; // Highest Priority MOb Register
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CANPAGE : byte absolute $00+$ED; // Page MOb Register
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CANSTMOB : byte absolute $00+$EE; // MOb Status Register
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CANCDMOB : byte absolute $00+$EF; // MOb Control and DLC Register
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CANIDT4 : byte absolute $00+$F0; // Identifier Tag Register 4
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CANIDT3 : byte absolute $00+$F1; // Identifier Tag Register 3
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CANIDT2 : byte absolute $00+$F2; // Identifier Tag Register 2
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CANIDT1 : byte absolute $00+$F3; // Identifier Tag Register 1
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CANIDM4 : byte absolute $00+$F4; // Identifier Mask Register 4
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CANIDM3 : byte absolute $00+$F5; // Identifier Mask Register 3
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CANIDM2 : byte absolute $00+$F6; // Identifier Mask Register 2
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CANIDM1 : byte absolute $00+$F7; // Identifier Mask Register 1
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CANSTML : byte absolute $00+$F8; // Time Stamp Register Low
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CANSTMH : byte absolute $00+$F9; // Time Stamp Register High
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CANMSG : byte absolute $00+$FA; // Message Data Register
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// ANALOG_COMPARATOR
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AC0CON : byte absolute $00+$94; // Analog Comparator 0 Control Register
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AC1CON : byte absolute $00+$95; // Analog Comparator 1 Control Register
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AC2CON : byte absolute $00+$96; // Analog Comparator 2 Control Register
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AC3CON : byte absolute $00+$97; // Analog Comparator 3 Control Register
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ACSR : byte absolute $00+$50; // Analog Comparator Status Register
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// DA_CONVERTER
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DACH : byte absolute $00+$92; // DAC Data Register High Byte
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DACL : byte absolute $00+$91; // DAC Data Register Low Byte
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DACON : byte absolute $00+$90; // DAC Control Register
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// CPU
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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SREG : byte absolute $00+$5F; // Status Register
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SP : word absolute $00+$5D; // Stack Pointer
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SPL : byte absolute $00+$5D; // Stack Pointer
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SPH : byte absolute $00+$5D+1; // Stack Pointer
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status Register
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OSCCAL : byte absolute $00+$66; // Oscillator Calibration Value
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CLKPR : byte absolute $00+$61; //
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SMCR : byte absolute $00+$53; // Sleep Mode Control Register
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GPIOR2 : byte absolute $00+$3A; // General Purpose IO Register 2
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GPIOR1 : byte absolute $00+$39; // General Purpose IO Register 1
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GPIOR0 : byte absolute $00+$3E; // General Purpose IO Register 0
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PLLCSR : byte absolute $00+$49; // PLL Control And Status Register
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PRR : byte absolute $00+$64; // Power Reduction Register
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// PORTE
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PORTE : byte absolute $00+$2E; // Port E Data Register
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DDRE : byte absolute $00+$2D; // Port E Data Direction Register
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PINE : byte absolute $00+$2C; // Port E Input Pins
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// TIMER_COUNTER_0
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TIMSK0 : byte absolute $00+$6E; // Timer/Counter0 Interrupt Mask Register
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TIFR0 : byte absolute $00+$35; // Timer/Counter0 Interrupt Flag register
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TCCR0A : byte absolute $00+$44; // Timer/Counter Control Register A
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TCCR0B : byte absolute $00+$45; // Timer/Counter Control Register B
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TCNT0 : byte absolute $00+$46; // Timer/Counter0
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OCR0A : byte absolute $00+$47; // Timer/Counter0 Output Compare Register
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OCR0B : byte absolute $00+$48; // Timer/Counter0 Output Compare Register
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GTCCR : byte absolute $00+$43; // General Timer/Counter Control Register
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// TIMER_COUNTER_1
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TIMSK1 : byte absolute $00+$6F; // Timer/Counter Interrupt Mask Register
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TIFR1 : byte absolute $00+$36; // Timer/Counter Interrupt Flag register
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TCCR1A : byte absolute $00+$80; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$81; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$82; // Timer/Counter1 Control Register C
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TCNT1 : word absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1L : byte absolute $00+$84; // Timer/Counter1 Bytes
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TCNT1H : byte absolute $00+$84+1; // Timer/Counter1 Bytes
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OCR1A : word absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AL : byte absolute $00+$88; // Timer/Counter1 Output Compare Register Bytes
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OCR1AH : byte absolute $00+$88+1; // Timer/Counter1 Output Compare Register Bytes
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OCR1B : word absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BL : byte absolute $00+$8A; // Timer/Counter1 Output Compare Register Bytes
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OCR1BH : byte absolute $00+$8A+1; // Timer/Counter1 Output Compare Register Bytes
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ICR1 : word absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1L : byte absolute $00+$86; // Timer/Counter1 Input Capture Register Bytes
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ICR1H : byte absolute $00+$86+1; // Timer/Counter1 Input Capture Register Bytes
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// AD_CONVERTER
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ADMUX : byte absolute $00+$7C; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$7A; // The ADC Control and Status register
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ADC : word absolute $00+$78; // ADC Data Register Bytes
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ADCL : byte absolute $00+$78; // ADC Data Register Bytes
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ADCH : byte absolute $00+$78+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$7B; // ADC Control and Status Register B
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DIDR0 : byte absolute $00+$7E; // Digital Input Disable Register 0
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DIDR1 : byte absolute $00+$7F; // Digital Input Disable Register 0
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AMP0CSR : byte absolute $00+$75; //
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AMP1CSR : byte absolute $00+$76; //
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AMP2CSR : byte absolute $00+$77; //
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// LINUART
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LINCR : byte absolute $00+$C8; // LIN Control Register
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LINSIR : byte absolute $00+$C9; // LIN Status and Interrupt Register
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LINENIR : byte absolute $00+$CA; // LIN Enable Interrupt Register
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LINERR : byte absolute $00+$CB; // LIN Error Register
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LINBTR : byte absolute $00+$CC; // LIN Bit Timing Register
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LINBRRL : byte absolute $00+$CD; // LIN Baud Rate Low Register
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LINBRRH : byte absolute $00+$CE; // LIN Baud Rate High Register
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LINDLR : byte absolute $00+$CF; // LIN Data Length Register
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LINIDR : byte absolute $00+$D0; // LIN Identifier Register
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LINSEL : byte absolute $00+$D1; // LIN Data Buffer Selection Register
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LINDAT : byte absolute $00+$D2; // LIN Data Register
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// SPI
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SPCR : byte absolute $00+$4C; // SPI Control Register
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SPSR : byte absolute $00+$4D; // SPI Status Register
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SPDR : byte absolute $00+$4E; // SPI Data Register
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// WATCHDOG
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WDTCSR : byte absolute $00+$60; // Watchdog Timer Control Register
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// EXTERNAL_INTERRUPT
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EICRA : byte absolute $00+$69; // External Interrupt Control Register
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EIMSK : byte absolute $00+$3D; // External Interrupt Mask Register
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EIFR : byte absolute $00+$3C; // External Interrupt Flag Register
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PCICR : byte absolute $00+$68; // Pin Change Interrupt Control Register
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PCMSK3 : byte absolute $00+$6D; // Pin Change Mask Register 3
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PCMSK2 : byte absolute $00+$6C; // Pin Change Mask Register 2
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PCMSK1 : byte absolute $00+$6B; // Pin Change Mask Register 1
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PCMSK0 : byte absolute $00+$6A; // Pin Change Mask Register 0
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PCIFR : byte absolute $00+$3B; // Pin Change Interrupt Flag Register
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// EEPROM
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EEAR : word absolute $00+$41; // EEPROM Read/Write Access
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EEARL : byte absolute $00+$41; // EEPROM Read/Write Access
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EEARH : byte absolute $00+$41+1; // EEPROM Read/Write Access
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EEDR : byte absolute $00+$40; // EEPROM Data Register
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EECR : byte absolute $00+$3F; // EEPROM Control Register
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const
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// CANGCON
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ABRQ = 7; // Abort Request
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OVRQ = 6; // Overload Frame Request
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TTC = 5; // Time Trigger Communication
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SYNTTC = 4; // Synchronization of TTC
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LISTEN = 3; // Listening Mode
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TEST = 2; // Test Mode
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ENASTB = 1; // Enable / Standby
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SWRES = 0; // Software Reset Request
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// CANGSTA
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OVFG = 6; // Overload Frame Flag
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TXBSY = 4; // Transmitter Busy
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RXBSY = 3; // Receiver Busy
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ENFG = 2; // Enable Flag
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BOFF = 1; // Bus Off Mode
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ERRP = 0; // Error Passive Mode
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// CANGIT
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CANIT = 7; // General Interrupt Flag
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BOFFIT = 6; // Bus Off Interrupt Flag
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OVRTIM = 5; // Overrun CAN Timer Flag
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BXOK = 4; // Burst Receive Interrupt Flag
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SERG = 3; // Stuff Error General Flag
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CERG = 2; // CRC Error General Flag
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FERG = 1; // Form Error General Flag
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AERG = 0; // Ackknowledgement Error General Flag
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// CANGIE
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ENIT = 7; // Enable all Interrupts
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ENBOFF = 6; // Enable Bus Off Interrupt
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ENRX = 5; // Enable Receive Interrupt
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ENTX = 4; // Enable Transmitt Interrupt
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ENERR = 3; // Enable MOb Error Interrupt
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ENBX = 2; // Enable Burst Receive Interrupt
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ENERG = 1; // Enable General Error Interrupt
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ENOVRT = 0; // Enable CAN Timer Overrun Interrupt
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// CANEN2
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ENMOB = 0; // Enable MObs
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// CANIE2
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IEMOB = 0; // Interrupt Enable MObs
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// CANSIT2
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SIT = 0; // Status of Interrupt MObs
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// CANBT1
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BRP = 1; // Baud Rate Prescaler bits
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// CANBT2
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SJW = 5; // Re-Sync Jump Width bits
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PRS = 1; // Propagation Time Segment bits
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// CANBT3
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PHS2 = 4; // Phase Segment 2 bits
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PHS1 = 1; // Phase Segment 1 bits
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SMP = 0; // Sample Type
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// CANHPMOB
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HPMOB = 4; // Highest Priority MOb Number bits
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CGP = 0; // CAN General Purpose bits
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// CANPAGE
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MOBNB = 4; // MOb Number bits
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AINC = 3; // MOb Data Buffer Auto Increment (Active Low)
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INDX = 0; // Data Buffer Index bits
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// CANSTMOB
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DLCW = 7; // Data Length Code Warning on MOb
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TXOK = 6; // Transmit OK on MOb
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RXOK = 5; // Receive OK on MOb
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BERR = 4; // Bit Error on MOb
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SERR = 3; // Stuff Error on MOb
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CERR = 2; // CRC Error on MOb
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FERR = 1; // Form Error on MOb
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AERR = 0; // Ackknowledgement Error on MOb
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// CANCDMOB
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CONMOB = 6; // MOb Config bits
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RPLV = 5; // Reply Valid
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IDE = 4; // Identifier Extension
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DLC = 0; // Data Length Code bits
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// CANIDT4
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IDT = 3; //
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RTRTAG = 2; //
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RB1TAG = 1; //
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RB0TAG = 0; //
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// AC0CON
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AC0EN = 7; // Analog Comparator 0 Enable Bit
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AC0IE = 6; // Analog Comparator 0 Interrupt Enable Bit
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AC0IS = 4; // Analog Comparator 0 Interrupt Select Bits
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ACCKSEL = 3; // Analog Comparator Clock Select
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AC0M = 0; // Analog Comparator 0 Multiplexer Register
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// AC1CON
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AC1EN = 7; // Analog Comparator 1 Enable Bit
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AC1IE = 6; // Analog Comparator 1 Interrupt Enable Bit
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AC1IS = 4; // Analog Comparator 1 Interrupt Select Bit
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AC1ICE = 3; // Analog Comparator 1 Interrupt Capture Enable Bit
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AC1M = 0; // Analog Comparator 1 Multiplexer Register
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// AC2CON
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AC2EN = 7; // Analog Comparator 2 Enable Bit
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AC2IE = 6; // Analog Comparator 2 Interrupt Enable Bit
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AC2IS = 4; // Analog Comparator 2 Interrupt Select Bit
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AC2M = 0; // Analog Comparator 2 Multiplexer Register
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// AC3CON
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AC3EN = 7; // Analog Comparator 3 Enable Bit
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AC3IE = 6; // Analog Comparator 3 Interrupt Enable Bit
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AC3IS = 4; // Analog Comparator 3 Interrupt Select Bit
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AC3M = 0; // Analog Comparator 3 Multiplexer Register
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// ACSR
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AC3IF = 7; // Analog Comparator 3 Interrupt Flag Bit
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AC2IF = 6; // Analog Comparator 2 Interrupt Flag Bit
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AC1IF = 5; // Analog Comparator 1 Interrupt Flag Bit
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AC0IF = 4; // Analog Comparator 0 Interrupt Flag Bit
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AC3O = 3; // Analog Comparator 3 Output Bit
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AC2O = 2; // Analog Comparator 2 Output Bit
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AC1O = 1; // Analog Comparator 1 Output Bit
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AC0O = 0; // Analog Comparator 0 Output Bit
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// DACH
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// DACL
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// DACON
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DAATE = 7; // DAC Auto Trigger Enable Bit
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DATS = 4; // DAC Trigger Selection Bits
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DALA = 2; // DAC Left Adjust
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DAEN = 0; // DAC Enable Bit
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// SPMCSR
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SPMIE = 7; // SPM Interrupt Enable
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RWWSB = 6; // Read While Write Section Busy
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SIGRD = 5; // Signature Row Read
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RWWSRE = 4; // Read While Write section read enable
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BLBSET = 3; // Boot Lock Bit Set
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// MCUCR
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SPIPS = 7; // SPI Pin Select
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PUD = 4; // Pull-up disable
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IVSEL = 1; // Interrupt Vector Select
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IVCE = 0; // Interrupt Vector Change Enable
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on reset flag
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// CLKPR
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CLKPCE = 7; //
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CLKPS = 0; //
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// SMCR
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SM = 1; // Sleep Mode Select bits
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SE = 0; // Sleep Enable
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// GPIOR2
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GPIOR = 0; // General Purpose IO Register 2 bis
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// GPIOR1
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// GPIOR0
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GPIOR07 = 7; // General Purpose IO Register 0 bit 7
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GPIOR06 = 6; // General Purpose IO Register 0 bit 6
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GPIOR05 = 5; // General Purpose IO Register 0 bit 5
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GPIOR04 = 4; // General Purpose IO Register 0 bit 4
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GPIOR03 = 3; // General Purpose IO Register 0 bit 3
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GPIOR02 = 2; // General Purpose IO Register 0 bit 2
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GPIOR01 = 1; // General Purpose IO Register 0 bit 1
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GPIOR00 = 0; // General Purpose IO Register 0 bit 0
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// PLLCSR
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PLLF = 2; // PLL Factor
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PLLE = 1; // PLL Enable
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PLOCK = 0; // PLL Lock Detector
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// PRR
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PRCAN = 6; // Power Reduction CAN
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PRPSC = 5; // Power Reduction PSC
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PRTIM1 = 4; // Power Reduction Timer/Counter1
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PRTIM0 = 3; // Power Reduction Timer/Counter0
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PRSPI = 2; // Power Reduction Serial Peripheral Interface
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PRLIN = 1; // Power Reduction LIN UART
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PRADC = 0; // Power Reduction ADC
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// TIMSK0
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OCIE0B = 2; // Timer/Counter0 Output Compare Match B Interrupt Enable
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OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable
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TOIE0 = 0; // Timer/Counter0 Overflow Interrupt Enable
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// TIFR0
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OCF0B = 2; // Timer/Counter0 Output Compare Flag 0B
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OCF0A = 1; // Timer/Counter0 Output Compare Flag 0A
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TOV0 = 0; // Timer/Counter0 Overflow Flag
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// TCCR0A
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COM0A = 6; // Compare Output Mode, Phase Correct PWM Mode
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COM0B = 4; // Compare Output Mode, Fast PWm
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WGM0 = 0; // Waveform Generation Mode
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; //
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CS0 = 0; // Clock Select
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// GTCCR
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TSM = 7; // Timer/Counter Synchronization Mode
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ICPSEL1 = 6; // Timer1 Input Capture Selection Bit
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PSR10 = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
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// TIMSK1
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ICIE1 = 5; // Timer/Counter1 Input Capture Interrupt Enable
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OCIE1B = 2; // Timer/Counter1 Output CompareB Match Interrupt Enable
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OCIE1A = 1; // Timer/Counter1 Output CompareA Match Interrupt Enable
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TOIE1 = 0; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR1
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ICF1 = 5; // Input Capture Flag 1
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OCF1B = 2; // Output Compare Flag 1B
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OCF1A = 1; // Output Compare Flag 1A
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TOV1 = 0; // Timer/Counter1 Overflow Flag
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Waveform Generation Mode
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Prescaler source of Timer/Counter 1
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// TCCR1C
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FOC1A = 7; //
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FOC1B = 6; //
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// GTCCR
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PSRSYNC = 0; // Prescaler Reset Timer/Counter1 and Timer/Counter0
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADHSM = 7; // ADC High Speed Mode
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ISRCEN = 6; // Current Source Enable
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AREFEN = 5; // Analog Reference pin Enable
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR0
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ADC7D = 7; // ADC7 Digital input Disable
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ADC6D = 6; // ADC6 Digital input Disable
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ADC5D = 5; // ADC5 Digital input Disable
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ADC4D = 4; // ADC4 Digital input Disable
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ADC3D = 3; // ADC3 Digital input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
|
|
// DIDR1
|
|
AMP2PD = 6; // AMP2P Pin Digital input Disable
|
|
ACMP0D = 5; // ACMP0 Pin Digital input Disable
|
|
AMP0PD = 4; // AMP0P Pin Digital input Disable
|
|
AMP0ND = 3; // AMP0N Pin Digital input Disable
|
|
ADC10D = 2; // ADC10 Pin Digital input Disable
|
|
ADC9D = 1; // ADC9 Pin Digital input Disable
|
|
ADC8D = 0; // ADC8 Pin Digital input Disable
|
|
// AMP0CSR
|
|
AMP0EN = 7; //
|
|
AMP0IS = 6; //
|
|
AMP0G = 4; //
|
|
AMPCMP0 = 3; // Amplifier 0 - Comparator 0 Connection
|
|
AMP0TS = 0; //
|
|
// AMP1CSR
|
|
AMP1EN = 7; //
|
|
AMP1IS = 6; //
|
|
AMP1G = 4; //
|
|
AMPCMP1 = 3; // Amplifier 1 - Comparator 1 Connection
|
|
AMP1TS = 0; //
|
|
// AMP2CSR
|
|
AMP2EN = 7; //
|
|
AMP2IS = 6; //
|
|
AMP2G = 4; //
|
|
AMPCMP2 = 3; // Amplifier 2 - Comparator 2 Connection
|
|
AMP2TS = 0; //
|
|
// LINCR
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|
LSWRES = 7; // Software Reset
|
|
LIN13 = 6; // LIN Standard
|
|
LCONF = 4; // LIN Configuration bits
|
|
LENA = 3; // LIN or UART Enable
|
|
LCMD = 0; // LIN Command and Mode bits
|
|
// LINSIR
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|
LIDST = 5; // Identifier Status bits
|
|
LBUSY = 4; // Busy Signal
|
|
LERR = 3; // Error Interrupt
|
|
LIDOK = 2; // Identifier Interrupt
|
|
LTXOK = 1; // Transmit Performed Interrupt
|
|
LRXOK = 0; // Receive Performed Interrupt
|
|
// LINENIR
|
|
LENERR = 3; // Enable Error Interrupt
|
|
LENIDOK = 2; // Enable Identifier Interrupt
|
|
LENTXOK = 1; // Enable Transmit Performed Interrupt
|
|
LENRXOK = 0; // Enable Receive Performed Interrupt
|
|
// LINERR
|
|
LABORT = 7; // Abort Flag
|
|
LTOERR = 6; // Frame Time Out Error Flag
|
|
LOVERR = 5; // Overrun Error Flag
|
|
LFERR = 4; // Framing Error Flag
|
|
LSERR = 3; // Synchronization Error Flag
|
|
LPERR = 2; // Parity Error Flag
|
|
LCERR = 1; // Checksum Error Flag
|
|
LBERR = 0; // Bit Error Flag
|
|
// LINBTR
|
|
LDISR = 7; // Disable Bit Timing Resynchronization
|
|
LBT = 0; // LIN Bit Timing bits
|
|
// LINBRRL
|
|
LDIV = 0; //
|
|
// LINBRRH
|
|
// LINDLR
|
|
LTXDL = 4; // LIN Transmit Data Length bits
|
|
LRXDL = 0; // LIN Receive Data Length bits
|
|
// LINIDR
|
|
LP = 6; // Parity bits
|
|
LID = 0; // Identifier bit 5 or Data Length bits
|
|
// LINSEL
|
|
LAINC = 3; // Auto Increment of Data Buffer Index (Active Low)
|
|
LINDX = 0; // FIFO LIN Data Buffer Index bits
|
|
// LINDAT
|
|
LDATA = 0; //
|
|
// SPCR
|
|
SPIE = 7; // SPI Interrupt Enable
|
|
SPE = 6; // SPI Enable
|
|
DORD = 5; // Data Order
|
|
MSTR = 4; // Master/Slave Select
|
|
CPOL = 3; // Clock polarity
|
|
CPHA = 2; // Clock Phase
|
|
SPR = 0; // SPI Clock Rate Selects
|
|
// SPSR
|
|
SPIF = 7; // SPI Interrupt Flag
|
|
WCOL = 6; // Write Collision Flag
|
|
SPI2X = 0; // Double SPI Speed Bit
|
|
// WDTCSR
|
|
WDIF = 7; // Watchdog Timeout Interrupt Flag
|
|
WDIE = 6; // Watchdog Timeout Interrupt Enable
|
|
WDP = 0; // Watchdog Timer Prescaler Bits
|
|
WDCE = 4; // Watchdog Change Enable
|
|
WDE = 3; // Watch Dog Enable
|
|
// EICRA
|
|
ISC3 = 6; // External Interrupt Sense Control Bit
|
|
ISC2 = 4; // External Interrupt Sense Control Bit
|
|
ISC1 = 2; // External Interrupt Sense Control 1 Bits
|
|
ISC0 = 0; // External Interrupt Sense Control 0 Bits
|
|
// EIMSK
|
|
INT = 0; // External Interrupt Request 3 Enable
|
|
// EIFR
|
|
INTF = 0; // External Interrupt Flags
|
|
// PCICR
|
|
PCIE = 0; // Pin Change Interrupt Enables
|
|
// PCMSK3
|
|
PCINT = 0; // Pin Change Enable Masks
|
|
// PCMSK2
|
|
// PCMSK1
|
|
// PCMSK0
|
|
// PCIFR
|
|
PCIF = 0; // Pin Change Interrupt Flags
|
|
// EECR
|
|
EEPM = 4; //
|
|
EERIE = 3; // EEProm Ready Interrupt Enable
|
|
EEMWE = 2; // EEPROM Master Write Enable
|
|
EEWE = 1; // EEPROM Write Enable
|
|
EERE = 0; // EEPROM Read Enable
|
|
|
|
implementation
|
|
|
|
{$i avrcommon.inc}
|
|
|
|
procedure ANACOMP0_ISR; external name 'ANACOMP0_ISR'; // Interrupt 1 Analog Comparator 0
|
|
procedure ANACOMP1_ISR; external name 'ANACOMP1_ISR'; // Interrupt 2 Analog Comparator 1
|
|
procedure ANACOMP2_ISR; external name 'ANACOMP2_ISR'; // Interrupt 3 Analog Comparator 2
|
|
procedure ANACOMP3_ISR; external name 'ANACOMP3_ISR'; // Interrupt 4 Analog Comparator 3
|
|
procedure PSC_FAULT_ISR; external name 'PSC_FAULT_ISR'; // Interrupt 5 PSC Fault
|
|
procedure PSC_EC_ISR; external name 'PSC_EC_ISR'; // Interrupt 6 PSC End of Cycle
|
|
procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 7 External Interrupt Request 0
|
|
procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 8 External Interrupt Request 1
|
|
procedure INT2_ISR; external name 'INT2_ISR'; // Interrupt 9 External Interrupt Request 2
|
|
procedure INT3_ISR; external name 'INT3_ISR'; // Interrupt 10 External Interrupt Request 3
|
|
procedure TIMER1_CAPT_ISR; external name 'TIMER1_CAPT_ISR'; // Interrupt 11 Timer/Counter1 Capture Event
|
|
procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 12 Timer/Counter1 Compare Match A
|
|
procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 13 Timer/Counter1 Compare Match B
|
|
procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 14 Timer1/Counter1 Overflow
|
|
procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 15 Timer/Counter0 Compare Match A
|
|
procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 16 Timer/Counter0 Compare Match B
|
|
procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 17 Timer/Counter0 Overflow
|
|
procedure CAN_INT_ISR; external name 'CAN_INT_ISR'; // Interrupt 18 CAN MOB, Burst, General Errors
|
|
procedure CAN_TOVF_ISR; external name 'CAN_TOVF_ISR'; // Interrupt 19 CAN Timer Overflow
|
|
procedure LIN_TC_ISR; external name 'LIN_TC_ISR'; // Interrupt 20 LIN Transfer Complete
|
|
procedure LIN_ERR_ISR; external name 'LIN_ERR_ISR'; // Interrupt 21 LIN Error
|
|
procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 22 Pin Change Interrupt Request 0
|
|
procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 23 Pin Change Interrupt Request 1
|
|
procedure PCINT2_ISR; external name 'PCINT2_ISR'; // Interrupt 24 Pin Change Interrupt Request 2
|
|
procedure PCINT3_ISR; external name 'PCINT3_ISR'; // Interrupt 25 Pin Change Interrupt Request 3
|
|
procedure SPI__STC_ISR; external name 'SPI__STC_ISR'; // Interrupt 26 SPI Serial Transfer Complete
|
|
procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 27 ADC Conversion Complete
|
|
procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 28 Watchdog Time-Out Interrupt
|
|
procedure EE_READY_ISR; external name 'EE_READY_ISR'; // Interrupt 29 EEPROM Ready
|
|
procedure SPM_READY_ISR; external name 'SPM_READY_ISR'; // Interrupt 30 Store Program Memory Read
|
|
|
|
procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
|
|
asm
|
|
jmp __dtors_end
|
|
jmp ANACOMP0_ISR
|
|
jmp ANACOMP1_ISR
|
|
jmp ANACOMP2_ISR
|
|
jmp ANACOMP3_ISR
|
|
jmp PSC_FAULT_ISR
|
|
jmp PSC_EC_ISR
|
|
jmp INT0_ISR
|
|
jmp INT1_ISR
|
|
jmp INT2_ISR
|
|
jmp INT3_ISR
|
|
jmp TIMER1_CAPT_ISR
|
|
jmp TIMER1_COMPA_ISR
|
|
jmp TIMER1_COMPB_ISR
|
|
jmp TIMER1_OVF_ISR
|
|
jmp TIMER0_COMPA_ISR
|
|
jmp TIMER0_COMPB_ISR
|
|
jmp TIMER0_OVF_ISR
|
|
jmp CAN_INT_ISR
|
|
jmp CAN_TOVF_ISR
|
|
jmp LIN_TC_ISR
|
|
jmp LIN_ERR_ISR
|
|
jmp PCINT0_ISR
|
|
jmp PCINT1_ISR
|
|
jmp PCINT2_ISR
|
|
jmp PCINT3_ISR
|
|
jmp SPI__STC_ISR
|
|
jmp ADC_ISR
|
|
jmp WDT_ISR
|
|
jmp EE_READY_ISR
|
|
jmp SPM_READY_ISR
|
|
|
|
.weak ANACOMP0_ISR
|
|
.weak ANACOMP1_ISR
|
|
.weak ANACOMP2_ISR
|
|
.weak ANACOMP3_ISR
|
|
.weak PSC_FAULT_ISR
|
|
.weak PSC_EC_ISR
|
|
.weak INT0_ISR
|
|
.weak INT1_ISR
|
|
.weak INT2_ISR
|
|
.weak INT3_ISR
|
|
.weak TIMER1_CAPT_ISR
|
|
.weak TIMER1_COMPA_ISR
|
|
.weak TIMER1_COMPB_ISR
|
|
.weak TIMER1_OVF_ISR
|
|
.weak TIMER0_COMPA_ISR
|
|
.weak TIMER0_COMPB_ISR
|
|
.weak TIMER0_OVF_ISR
|
|
.weak CAN_INT_ISR
|
|
.weak CAN_TOVF_ISR
|
|
.weak LIN_TC_ISR
|
|
.weak LIN_ERR_ISR
|
|
.weak PCINT0_ISR
|
|
.weak PCINT1_ISR
|
|
.weak PCINT2_ISR
|
|
.weak PCINT3_ISR
|
|
.weak SPI__STC_ISR
|
|
.weak ADC_ISR
|
|
.weak WDT_ISR
|
|
.weak EE_READY_ISR
|
|
.weak SPM_READY_ISR
|
|
|
|
.set ANACOMP0_ISR, Default_IRQ_handler
|
|
.set ANACOMP1_ISR, Default_IRQ_handler
|
|
.set ANACOMP2_ISR, Default_IRQ_handler
|
|
.set ANACOMP3_ISR, Default_IRQ_handler
|
|
.set PSC_FAULT_ISR, Default_IRQ_handler
|
|
.set PSC_EC_ISR, Default_IRQ_handler
|
|
.set INT0_ISR, Default_IRQ_handler
|
|
.set INT1_ISR, Default_IRQ_handler
|
|
.set INT2_ISR, Default_IRQ_handler
|
|
.set INT3_ISR, Default_IRQ_handler
|
|
.set TIMER1_CAPT_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER1_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER1_OVF_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPA_ISR, Default_IRQ_handler
|
|
.set TIMER0_COMPB_ISR, Default_IRQ_handler
|
|
.set TIMER0_OVF_ISR, Default_IRQ_handler
|
|
.set CAN_INT_ISR, Default_IRQ_handler
|
|
.set CAN_TOVF_ISR, Default_IRQ_handler
|
|
.set LIN_TC_ISR, Default_IRQ_handler
|
|
.set LIN_ERR_ISR, Default_IRQ_handler
|
|
.set PCINT0_ISR, Default_IRQ_handler
|
|
.set PCINT1_ISR, Default_IRQ_handler
|
|
.set PCINT2_ISR, Default_IRQ_handler
|
|
.set PCINT3_ISR, Default_IRQ_handler
|
|
.set SPI__STC_ISR, Default_IRQ_handler
|
|
.set ADC_ISR, Default_IRQ_handler
|
|
.set WDT_ISR, Default_IRQ_handler
|
|
.set EE_READY_ISR, Default_IRQ_handler
|
|
.set SPM_READY_ISR, Default_IRQ_handler
|
|
end;
|
|
|
|
end.
|