mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 21:28:14 +02:00
309 lines
12 KiB
ObjectPascal
309 lines
12 KiB
ObjectPascal
unit ATtiny20;
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interface
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var
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// PORTB
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PORTCR : byte absolute $00+$08; // Port Control Register
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PUEB : byte absolute $00+$07; // Pull-up Enable Control Register
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DDRB : byte absolute $00+$05; // Data Direction Register, Port B
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PINB : byte absolute $00+$04; // Port B Data register
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PORTB : byte absolute $00+$06; // Input Pins, Port B
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// WATCHDOG
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WDTCSR : byte absolute $00+$31; // Watchdog Timer Control and Status Register
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// AD_CONVERTER
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ADMUX : byte absolute $00+$10; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$12; // The ADC Control and Status register
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ADC : word absolute $00+$0E; // ADC Data Register Bytes
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ADCL : byte absolute $00+$0E; // ADC Data Register Bytes
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ADCH : byte absolute $00+$0E+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$11; // ADC Control and Status Register B
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DIDR0 : byte absolute $00+$0D; // Digital Input Disable Register 0
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// ANALOG_COMPARATOR
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ACSRB : byte absolute $00+$13; // Analog Comparator Control And Status Register B
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ACSRA : byte absolute $00+$14; // Analog Comparator Control And Status Register A
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// CPU
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CCP : byte absolute $00+$3C; // Configuration Change Protection
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SP : word absolute $00+$3D; // Stack Pointer
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SPL : byte absolute $00+$3D; // Stack Pointer
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SPH : byte absolute $00+$3D+1; // Stack Pointer
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SREG : byte absolute $00+$3F; // Status Register
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CLKMSR : byte absolute $00+$37; // Clock Main Settings Register
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CLKPSR : byte absolute $00+$36; // Clock Prescale Register
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OSCCAL : byte absolute $00+$39; // Oscillator Calibration Value
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PRR : byte absolute $00+$35; // Power Reduction Register
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RSTFLR : byte absolute $00+$3B; // Reset Flag Register
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NVMCSR : byte absolute $00+$32; // Non-Volatile Memory Control and Status Register
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NVMCMD : byte absolute $00+$33; // Non-Volatile Memory Command
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MCUCR : byte absolute $00+$3A; // MCU Control Register
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// EXTERNAL_INTERRUPT
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PCMSK1 : byte absolute $00+$0A; // Pin Change Mask Register 1
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PCMSK0 : byte absolute $00+$09; // Pin Change Mask Register 0
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GIFR : byte absolute $00+$0B; // General Interrupt Flag Register
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GIMSK : byte absolute $00+$0C; // General Interrupt Mask Register
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// TIMER_COUNTER_0
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TCCR0A : byte absolute $00+$19; // Timer/Counter 0 Control Register A
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TCCR0B : byte absolute $00+$18; // Timer/Counter 0 Control Register B
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TIMSK : byte absolute $00+$26; // Timer Interrupt Mask Register
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TIFR : byte absolute $00+$25; // Overflow Interrupt Enable
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GTCCR : byte absolute $00+$27; // General Timer/Counter Control Register
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TCNT0 : byte absolute $00+$17; // Timer/Counter0
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OCR0A : byte absolute $00+$16; // Timer/Counter0 Output Compare Register
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OCR0B : byte absolute $00+$15; // Timer/Counter0 Output Compare Register
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// TWI
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TWSCRA : byte absolute $00+$2D; // TWI Slave Control Register A
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TWSCRB : byte absolute $00+$2C; // TWI Slave Control Register B
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TWSSRA : byte absolute $00+$2B; // TWI Slave Status Register A
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TWSA : byte absolute $00+$2A; // TWI Slave Address Register
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TWSD : byte absolute $00+$28; // TWI Slave Data Register
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TWSAM : byte absolute $00+$29; // TWI Slave Address Mask Register
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// PORTA
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PUEA : byte absolute $00+$03; // Pull-up Enable Control Register
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PORTA : byte absolute $00+$02; // Port A Data Register
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DDRA : byte absolute $00+$01; // Data Direction Register, Port A
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PINA : byte absolute $00+$00; // Port A Input Pins
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$24; // Timer/Counter1 Control Register A
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TCCR1B : byte absolute $00+$23; // Timer/Counter1 Control Register B
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TCCR1C : byte absolute $00+$22; // Timer/Counter1 Control Register C
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TCNT1 : word absolute $00+$20; // Timer/Counter1
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TCNT1L : byte absolute $00+$20; // Timer/Counter1
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TCNT1H : byte absolute $00+$20+1; // Timer/Counter1
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OCR1A : word absolute $00+$1E; // Timer/Counter 1 Output Compare Register A
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OCR1AL : byte absolute $00+$1E; // Timer/Counter 1 Output Compare Register A
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OCR1AH : byte absolute $00+$1E+1; // Timer/Counter 1 Output Compare Register A
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OCR1B : word absolute $00+$1C; // Timer/Counter1 Output Compare Register B
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OCR1BL : byte absolute $00+$1C; // Timer/Counter1 Output Compare Register B
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OCR1BH : byte absolute $00+$1C+1; // Timer/Counter1 Output Compare Register B
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ICR1 : word absolute $00+$1A; // Input Capture Register Bytes
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ICR1L : byte absolute $00+$1A; // Input Capture Register Bytes
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ICR1H : byte absolute $00+$1A+1; // Input Capture Register Bytes
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// SPI
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SPCR : byte absolute $00+$30; // SPI Control Register
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SPSR : byte absolute $00+$2F; // SPI Status Register
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SPDR : byte absolute $00+$2E; // SPI Data Register
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const
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// PORTCR
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BBMB = 1; // Break-Before-Make Mode Enable
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// WDTCSR
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WDIF = 7; // Watchdog Timer Interrupt Flag
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WDIE = 6; // Watchdog Timer Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDE = 3; // Watch Dog Enable
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// ADMUX
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REFS = 6; // Reference Selection Bit
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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ADLAR = 3; //
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR0
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ADC7D = 7; // ADC6 Digital input Disable
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ADC6D = 6; // ADC5 Digital input Disable
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ADC5D = 5; // ADC4 Digital input Disable
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ADC4D = 4; // ADC3 Digital input Disable
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ADC3D = 3; // AREF Digital Input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
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// ACSRB
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HSEL = 7; // Hysteresis Select
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HLEV = 6; // Hysteresis Level
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ACME = 2; // Analog Comparator Multiplexer Enable
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// ACSRA
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACIC = 2; // Analog Comparator Input Capture Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// CLKMSR
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CLKMS = 0; // Clock Main Select Bits
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// CLKPSR
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CLKPS = 0; // Clock Prescaler Select Bits
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// PRR
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PRTWI = 4; // Power Reduction TWI
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PRSPI = 3; // Power Reduction Serial Peripheral Interface
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PRTIM1 = 2; // Power Reduction Timer/Counter1
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PRTIM0 = 1; // Power Reduction Timer/Counter0
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PRADC = 0; // Power Reduction ADC
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// RSTFLR
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WDRF = 3; // Watchdog Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-on Reset Flag
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// NVMCSR
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NVMBSY = 7; // Non-Volatile Memory Busy
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// PCMSK1
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PCINT = 0; // Pin Change Enable Masks
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// PCMSK0
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// GIFR
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PCIF = 4; // Pin Change Interrupt Flags
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INTF0 = 0; // External Interrupt Flag 0
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// GIMSK
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PCIE = 4; // Pin Change Interrupt Enables
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INT0 = 0; // External Interrupt Request 0 Enable
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// TCCR0A
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COM0A = 6; // Compare Output Mode for Channel A bits
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COM0B = 4; // Compare Output Mode for Channel B bits
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WGM0 = 0; // Waveform Generation Mode
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// TCCR0B
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FOC0A = 7; // Force Output Compare A
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FOC0B = 6; // Force Output Compare B
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WGM02 = 3; // Waveform Generation Mode
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CS0 = 0; // Clock Select
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// TIMSK
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ICIE1 = 7; // Input Capture Interrupt Enable
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OCIE1B = 5; // Output Compare B Match Interrupt Enable
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OCIE1A = 4; // Output Compare A Match Interrupt Enable
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TOIE = 0; // Overflow Interrupt Enable
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OCIE0B = 2; // Timer/Counter Output Compare Match B Interrupt Enable
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OCIE0A = 1; // Timer/Counter0 Output Compare Match A Interrupt Enable
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// TIFR
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ICF1 = 7; // Input Capture Flag
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OCF1B = 5; // Timer Output Compare Flag 1B
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OCF1A = 4; // Timer Output Compare Flag 1A
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TOV = 0; // Timer Overflow Flag
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OCF0B = 2; // Output Compare Flag 0 B
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OCF0A = 1; // Output Compare Flag 0 A
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// GTCCR
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TSM = 7; // Timer Synchronization Mode
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PSR = 0; // Prescaler Reset
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// TWSCRA
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TWSHE = 7; // TWI SDA Hold Time Enable
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TWDIE = 5; // TWI Data Interrupt Enable
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TWASIE = 4; // TWI Address/Stop Interrupt Enable
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TWEN = 3; // Two-Wire Interface Enable
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TWSIE = 2; // TWI Stop Interrupt Enable
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TWPME = 1; // TWI Promiscuous Mode Enable
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TWSME = 0; // TWI Smart Mode Enable
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// TWSCRB
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TWAA = 2; // TWI Acknowledge Action
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TWCMD = 0; //
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// TWSA
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// TWSD
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// PORTCR
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BBMA = 0; // Break-Before-Make Mode Enable
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// TCCR1A
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COM1A = 6; // Compare Output Mode 1A, bits
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COM1B = 4; // Compare Output Mode 1B, bits
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WGM1 = 0; // Waveform Generation Mode Bits
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// TCCR1B
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ICNC1 = 7; // Input Capture 1 Noise Canceler
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ICES1 = 6; // Input Capture 1 Edge Select
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CS1 = 0; // Clock Select1 bits
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// TCCR1C
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FOC1A = 7; // Force Output Compare for channel A
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FOC1B = 6; // Force Output Compare for channel B
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// TIMSK
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// TIFR
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// GTCCR
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// SPCR
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SPIE = 7; // SPI Interrupt Enable
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SPE = 6; // SPI Enable
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DORD = 5; // Data Order
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MSTR = 4; // Master/Slave Select
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CPOL = 3; // Clock polarity
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CPHA = 2; // Clock Phase
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SPR = 0; // SPI Clock Rate Selects
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// SPSR
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SPIF = 7; // SPI Interrupt Flag
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WCOL = 6; // Write Collision Flag
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SPI2X = 0; // Double SPI Speed Bit
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt Request 0
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procedure PCINT0_ISR; external name 'PCINT0_ISR'; // Interrupt 2 Pin Change Interrupt Request 0
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procedure PCINT1_ISR; external name 'PCINT1_ISR'; // Interrupt 3 Pin Change Interrupt Request 1
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 4 Watchdog Time-out
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procedure TIM1_CAPT_ISR; external name 'TIM1_CAPT_ISR'; // Interrupt 5 Timer/Counter1 Input Capture
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procedure TIM1_COMPA_ISR; external name 'TIM1_COMPA_ISR'; // Interrupt 6 Timer/Counter1 Compare Match A
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procedure TIM1_COMPB_ISR; external name 'TIM1_COMPB_ISR'; // Interrupt 7 Timer/Counter1 Compare Match B
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procedure TIM1_OVF_ISR; external name 'TIM1_OVF_ISR'; // Interrupt 8 Timer/Counter1 Overflow
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procedure TIM0_COMPA_ISR; external name 'TIM0_COMPA_ISR'; // Interrupt 9 Timer/Counter0 Compare Match A
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procedure TIM0_COMPB_ISR; external name 'TIM0_COMPB_ISR'; // Interrupt 10 Timer/Counter0 Compare Match B
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procedure TIM0_OVF_ISR; external name 'TIM0_OVF_ISR'; // Interrupt 11 Timer/Counter0 Overflow
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 12 Analog Comparator
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procedure ADC_ADC_ISR; external name 'ADC_ADC_ISR'; // Interrupt 13 Conversion Complete
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procedure TWI_SLAVE_ISR; external name 'TWI_SLAVE_ISR'; // Interrupt 14 Two-Wire Interface
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procedure SPI_ISR; external name 'SPI_ISR'; // Interrupt 15 Serial Peripheral Interface
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procedure QTRIP_ISR; external name 'QTRIP_ISR'; // Interrupt 16 Touch Sensing
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp PCINT0_ISR
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rjmp PCINT1_ISR
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rjmp WDT_ISR
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rjmp TIM1_CAPT_ISR
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rjmp TIM1_COMPA_ISR
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rjmp TIM1_COMPB_ISR
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rjmp TIM1_OVF_ISR
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rjmp TIM0_COMPA_ISR
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rjmp TIM0_COMPB_ISR
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rjmp TIM0_OVF_ISR
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rjmp ANA_COMP_ISR
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rjmp ADC_ADC_ISR
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rjmp TWI_SLAVE_ISR
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rjmp SPI_ISR
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rjmp QTRIP_ISR
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.weak INT0_ISR
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.weak PCINT0_ISR
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.weak PCINT1_ISR
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.weak WDT_ISR
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.weak TIM1_CAPT_ISR
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.weak TIM1_COMPA_ISR
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.weak TIM1_COMPB_ISR
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.weak TIM1_OVF_ISR
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.weak TIM0_COMPA_ISR
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.weak TIM0_COMPB_ISR
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.weak TIM0_OVF_ISR
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.weak ANA_COMP_ISR
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.weak ADC_ADC_ISR
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.weak TWI_SLAVE_ISR
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.weak SPI_ISR
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.weak QTRIP_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT0_ISR, Default_IRQ_handler
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.set PCINT1_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set TIM1_CAPT_ISR, Default_IRQ_handler
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.set TIM1_COMPA_ISR, Default_IRQ_handler
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.set TIM1_COMPB_ISR, Default_IRQ_handler
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.set TIM1_OVF_ISR, Default_IRQ_handler
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.set TIM0_COMPA_ISR, Default_IRQ_handler
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.set TIM0_COMPB_ISR, Default_IRQ_handler
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.set TIM0_OVF_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set ADC_ADC_ISR, Default_IRQ_handler
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.set TWI_SLAVE_ISR, Default_IRQ_handler
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.set SPI_ISR, Default_IRQ_handler
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.set QTRIP_ISR, Default_IRQ_handler
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end;
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end.
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