mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-08 19:28:13 +02:00
355 lines
14 KiB
ObjectPascal
355 lines
14 KiB
ObjectPascal
unit ATtiny461A;
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interface
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var
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// PORTA
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PORTA : byte absolute $00+$3B; // Port A Data Register
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DDRA : byte absolute $00+$3A; // Port A Data Direction Register
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PINA : byte absolute $00+$39; // Port A Input Pins
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// PORTB
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PORTB : byte absolute $00+$38; // Port B Data Register
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DDRB : byte absolute $00+$37; // Port B Data Direction Register
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PINB : byte absolute $00+$36; // Port B Input Pins
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// AD_CONVERTER
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ADMUX : byte absolute $00+$27; // The ADC multiplexer Selection Register
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ADCSRA : byte absolute $00+$26; // The ADC Control and Status register
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ADC : word absolute $00+$24; // ADC Data Register Bytes
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ADCL : byte absolute $00+$24; // ADC Data Register Bytes
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ADCH : byte absolute $00+$24+1; // ADC Data Register Bytes
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ADCSRB : byte absolute $00+$23; // ADC Control and Status Register B
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DIDR1 : byte absolute $00+$22; // Digital Input Disable Register 1
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DIDR0 : byte absolute $00+$21; // Digital Input Disable Register 0
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// ANALOG_COMPARATOR
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ACSRB : byte absolute $00+$29; // Analog Comparator Control And Status Register B
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ACSRA : byte absolute $00+$28; // Analog Comparator Control And Status Register A
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// USI
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USIPP : byte absolute $00+$31; // USI Pin Position
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USIBR : byte absolute $00+$30; // USI Buffer Register
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USIDR : byte absolute $00+$2F; // USI Data Register
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USISR : byte absolute $00+$2E; // USI Status Register
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USICR : byte absolute $00+$2D; // USI Control Register
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// EEPROM
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EEAR : word absolute $00+$3E; // EEPROM Address Register Bytes
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EEARL : byte absolute $00+$3E; // EEPROM Address Register Bytes
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EEARH : byte absolute $00+$3E+1; // EEPROM Address Register Bytes
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EEDR : byte absolute $00+$3D; // EEPROM Data Register
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EECR : byte absolute $00+$3C; // EEPROM Control Register
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// WATCHDOG
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WDTCR : byte absolute $00+$41; // Watchdog Timer Control Register
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// TIMER_COUNTER_0
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TIMSK : byte absolute $00+$59; // Timer/Counter Interrupt Mask Register
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TIFR : byte absolute $00+$58; // Timer/Counter0 Interrupt Flag register
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TCCR0A : byte absolute $00+$35; // Timer/Counter Control Register A
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TCCR0B : byte absolute $00+$53; // Timer/Counter Control Register B
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TCNT0H : byte absolute $00+$34; // Timer/Counter0 High
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TCNT0L : byte absolute $00+$52; // Timer/Counter0 Low
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OCR0A : byte absolute $00+$33; // Timer/Counter0 Output Compare Register
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OCR0B : byte absolute $00+$32; // Timer/Counter0 Output Compare Register
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// TIMER_COUNTER_1
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TCCR1A : byte absolute $00+$50; // Timer/Counter Control Register A
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TCCR1B : byte absolute $00+$4F; // Timer/Counter Control Register B
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TCCR1C : byte absolute $00+$47; // Timer/Counter Control Register C
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TCCR1D : byte absolute $00+$46; // Timer/Counter Control Register D
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TCCR1E : byte absolute $00+$20; // Timer/Counter1 Control Register E
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TCNT1 : byte absolute $00+$4E; // Timer/Counter Register
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TC1H : byte absolute $00+$45; // Timer/Counter 1 Register High
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OCR1A : byte absolute $00+$4D; // Output Compare Register
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OCR1B : byte absolute $00+$4C; // Output Compare Register
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OCR1C : byte absolute $00+$4B; // Output compare register
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OCR1D : byte absolute $00+$4A; // Output compare register
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DT1 : byte absolute $00+$44; // Timer/Counter 1 Dead Time Value
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// BOOT_LOAD
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SPMCSR : byte absolute $00+$57; // Store Program Memory Control Register
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// CPU
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SREG : byte absolute $00+$5F; // Status Register
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PRR : byte absolute $00+$56; // Power Reduction Register
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SP : word absolute $00+$5D; // Stack Pointer Bytes
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SPL : byte absolute $00+$5D; // Stack Pointer Bytes
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SPH : byte absolute $00+$5D+1; // Stack Pointer Bytes
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MCUCR : byte absolute $00+$55; // MCU Control Register
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MCUSR : byte absolute $00+$54; // MCU Status register
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OSCCAL : byte absolute $00+$51; // Oscillator Calibration Register
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CLKPR : byte absolute $00+$48; // Clock Prescale Register
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PLLCSR : byte absolute $00+$49; // PLL Control and status register
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DWDR : byte absolute $00+$40; // debugWire data register
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GPIOR2 : byte absolute $00+$2C; // General Purpose IO register 2
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GPIOR1 : byte absolute $00+$2B; // General Purpose register 1
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GPIOR0 : byte absolute $00+$2A; // General purpose register 0
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// EXTERNAL_INTERRUPT
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GIMSK : byte absolute $00+$5B; // General Interrupt Mask Register
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GIFR : byte absolute $00+$5A; // General Interrupt Flag register
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PCMSK1 : byte absolute $00+$42; // Pin Change Enable Mask 1
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PCMSK0 : byte absolute $00+$43; // Pin Change Enable Mask 0
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const
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// ADMUX
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REFS = 6; // Reference Selection Bits
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ADLAR = 5; // Left Adjust Result
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MUX = 0; // Analog Channel and Gain Selection Bits
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// ADCSRA
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ADEN = 7; // ADC Enable
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ADSC = 6; // ADC Start Conversion
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ADATE = 5; // ADC Auto Trigger Enable
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ADIF = 4; // ADC Interrupt Flag
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ADIE = 3; // ADC Interrupt Enable
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ADPS = 0; // ADC Prescaler Select Bits
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// ADCSRB
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BIN = 7; // Bipolar Input Mode
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GSEL = 6; // Gain Select
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IPR = 5; // Input Polarity Mode
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REFS2 = 4; //
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MUX5 = 3; //
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ADTS = 0; // ADC Auto Trigger Sources
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// DIDR1
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ADC10D = 7; // ADC10 Digital input Disable
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ADC9D = 6; // ADC9 Digital input Disable
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ADC8D = 5; // ADC8 Digital input Disable
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ADC7D = 4; // ADC7 Digital input Disable
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// DIDR0
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ADC6D = 7; // ADC6 Digital input Disable
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ADC5D = 6; // ADC5 Digital input Disable
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ADC4D = 5; // ADC4 Digital input Disable
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ADC3D = 4; // ADC3 Digital input Disable
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AREFD = 3; // AREF Digital Input Disable
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ADC2D = 2; // ADC2 Digital input Disable
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ADC1D = 1; // ADC1 Digital input Disable
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ADC0D = 0; // ADC0 Digital input Disable
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// ACSRB
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HSEL = 7; // Hysteresis Select
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HLEV = 6; // Hysteresis Level
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ACM = 0; // Analog Comparator Multiplexer
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// ACSRA
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ACD = 7; // Analog Comparator Disable
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ACBG = 6; // Analog Comparator Bandgap Select
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ACO = 5; // Analog Compare Output
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ACI = 4; // Analog Comparator Interrupt Flag
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ACIE = 3; // Analog Comparator Interrupt Enable
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ACME = 2; // Analog Comparator Multiplexer Enable
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ACIS = 0; // Analog Comparator Interrupt Mode Select bits
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// USISR
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USISIF = 7; // Start Condition Interrupt Flag
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USIOIF = 6; // Counter Overflow Interrupt Flag
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USIPF = 5; // Stop Condition Flag
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USIDC = 4; // Data Output Collision
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USICNT = 0; // USI Counter Value Bits
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// USICR
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USISIE = 7; // Start Condition Interrupt Enable
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USIOIE = 6; // Counter Overflow Interrupt Enable
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USIWM = 4; // USI Wire Mode Bits
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USICS = 2; // USI Clock Source Select Bits
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USICLK = 1; // Clock Strobe
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USITC = 0; // Toggle Clock Port Pin
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// EECR
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EEPM = 4; // EEPROM Programming Mode Bits
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EERIE = 3; // EEPROM Ready Interrupt Enable
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EEMPE = 2; // EEPROM Master Write Enable
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EEPE = 1; // EEPROM Write Enable
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EERE = 0; // EEPROM Read Enable
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// WDTCR
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WDIF = 7; // Watchdog Timeout Interrupt Flag
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WDIE = 6; // Watchdog Timeout Interrupt Enable
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WDP = 0; // Watchdog Timer Prescaler Bits
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WDCE = 4; // Watchdog Change Enable
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WDE = 3; // Watch Dog Enable
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// TIMSK
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OCIE0A = 4; // Timer/Counter0 Output Compare Match A Interrupt Enable
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OCIE0B = 3; // Timer/Counter0 Output Compare Match B Interrupt Enable
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TOIE0 = 1; // Timer/Counter0 Overflow Interrupt Enable
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TICIE0 = 0; // Timer/Counter0 Input Capture Interrupt Enable
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// TIFR
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OCF0A = 4; // Timer/Counter0 Output Compare Flag 0A
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OCF0B = 3; // Timer/Counter0 Output Compare Flag 0B
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TOV0 = 1; // Timer/Counter0 Overflow Flag
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ICF0 = 0; // Timer/Counter0 Input Capture Flag
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// TCCR0A
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TCW0 = 7; // Timer/Counter 0 Width
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ICEN0 = 6; // Input Capture Mode Enable
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ICNC0 = 5; // Input Capture Noice Canceler
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ICES0 = 4; // Input Capture Edge Select
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ACIC0 = 3; // Analog Comparator Input Capture Enable
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WGM00 = 0; // Waveform Generation Mode
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// TCCR0B
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TSM = 4; // Timer/Counter Synchronization Mode
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PSR0 = 3; // Timer/Counter 0 Prescaler Reset
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CS0 = 0; // Clock Select
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// TCCR1A
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COM1A = 6; // Compare Output Mode, Bits
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COM1B = 4; // Compare Output Mode, Bits
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FOC1A = 3; // Force Output Compare Match 1A
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FOC1B = 2; // Force Output Compare Match 1B
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PWM1A = 1; // Pulse Width Modulator Enable
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PWM1B = 0; // Pulse Width Modulator Enable
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// TCCR1B
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PSR1 = 6; // Timer/Counter 1 Prescaler reset
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DTPS1 = 4; // Dead Time Prescaler
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CS1 = 0; // Clock Select Bits
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// TCCR1C
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COM1A1S = 7; // COM1A1 Shadow Bit
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COM1A0S = 6; // COM1A0 Shadow Bit
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COM1B1S = 5; // COM1B1 Shadow Bit
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COM1B0S = 4; // COM1B0 Shadow Bit
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COM1D = 2; // Comparator D output mode
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FOC1D = 1; // Force Output Compare Match 1D
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PWM1D = 0; // Pulse Width Modulator D Enable
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// TCCR1D
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FPIE1 = 7; // Fault Protection Interrupt Enable
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FPEN1 = 6; // Fault Protection Mode Enable
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FPNC1 = 5; // Fault Protection Noise Canceler
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FPES1 = 4; // Fault Protection Edge Select
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FPAC1 = 3; // Fault Protection Analog Comparator Enable
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FPF1 = 2; // Fault Protection Interrupt Flag
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WGM1 = 0; // Waveform Generation Mode Bit
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// TCCR1E
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OC1OE = 0; // Ouput Compare Override Enable Bits
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// TIMSK
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OCIE1D = 7; // OCIE1D: Timer/Counter1 Output Compare Interrupt Enable
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OCIE1A = 6; // OCIE1A: Timer/Counter1 Output Compare Interrupt Enable
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OCIE1B = 5; // OCIE1A: Timer/Counter1 Output Compare B Interrupt Enable
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TOIE1 = 2; // Timer/Counter1 Overflow Interrupt Enable
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// TIFR
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OCF1D = 7; // Timer/Counter1 Output Compare Flag 1D
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OCF1A = 6; // Timer/Counter1 Output Compare Flag 1A
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OCF1B = 5; // Timer/Counter1 Output Compare Flag 1B
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TOV1 = 2; // Timer/Counter1 Overflow Flag
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// DT1
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DT1H = 4; //
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DT1L = 0; //
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// SPMCSR
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CTPB = 4; // Clear temporary page buffer
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RFLB = 3; // Read fuse and lock bits
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PGWRT = 2; // Page Write
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PGERS = 1; // Page Erase
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SPMEN = 0; // Store Program Memory Enable
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// SREG
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I = 7; // Global Interrupt Enable
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T = 6; // Bit Copy Storage
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H = 5; // Half Carry Flag
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S = 4; // Sign Bit
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V = 3; // Two's Complement Overflow Flag
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N = 2; // Negative Flag
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Z = 1; // Zero Flag
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C = 0; // Carry Flag
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// PRR
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PRTIM1 = 3; // Power Reduction Timer/Counter1
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PRTIM0 = 2; // Power Reduction Timer/Counter0
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PRUSI = 1; // Power Reduction USI
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PRADC = 0; // Power Reduction ADC
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// MCUCR
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BODS = 7; // BOD Sleep
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PUD = 6; // Pull-up Disable
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SE = 5; // Sleep Enable
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SM = 3; // Sleep Mode Select Bits
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BODSE = 2; // BOD Sleep Enable
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ISC0 = 0; // Interrupt Sense Control 0 bits
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// MCUSR
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WDRF = 3; // Watchdog Reset Flag
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BORF = 2; // Brown-out Reset Flag
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EXTRF = 1; // External Reset Flag
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PORF = 0; // Power-On Reset Flag
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// CLKPR
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CLKPCE = 7; // Clock Prescaler Change Enable
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CLKPS = 0; // Clock Prescaler Select Bits
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// PLLCSR
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LSM = 7; // Low speed mode
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PCKE = 2; // PCK Enable
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PLLE = 1; // PLL Enable
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PLOCK = 0; // PLL Lock detector
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// MCUCR
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ISC01 = 1; // Interrupt Sense Control 0 Bit 1
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ISC00 = 0; // Interrupt Sense Control 0 Bit 0
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// GIMSK
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INT = 6; // External Interrupt Request 1 Enable
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PCIE = 4; // Pin Change Interrupt Enables
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// GIFR
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INTF = 6; // External Interrupt Flags
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PCIF = 5; // Pin Change Interrupt Flag
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implementation
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{$define RELBRANCHES}
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{$i avrcommon.inc}
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procedure INT0_ISR; external name 'INT0_ISR'; // Interrupt 1 External Interrupt 0
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procedure PCINT_ISR; external name 'PCINT_ISR'; // Interrupt 2 Pin Change Interrupt
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procedure TIMER1_COMPA_ISR; external name 'TIMER1_COMPA_ISR'; // Interrupt 3 Timer/Counter1 Compare Match 1A
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procedure TIMER1_COMPB_ISR; external name 'TIMER1_COMPB_ISR'; // Interrupt 4 Timer/Counter1 Compare Match 1B
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procedure TIMER1_OVF_ISR; external name 'TIMER1_OVF_ISR'; // Interrupt 5 Timer/Counter1 Overflow
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procedure TIMER0_OVF_ISR; external name 'TIMER0_OVF_ISR'; // Interrupt 6 Timer/Counter0 Overflow
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procedure USI_START_ISR; external name 'USI_START_ISR'; // Interrupt 7 USI Start
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procedure USI_OVF_ISR; external name 'USI_OVF_ISR'; // Interrupt 8 USI Overflow
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procedure EE_RDY_ISR; external name 'EE_RDY_ISR'; // Interrupt 9 EEPROM Ready
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procedure ANA_COMP_ISR; external name 'ANA_COMP_ISR'; // Interrupt 10 Analog Comparator
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procedure ADC_ISR; external name 'ADC_ISR'; // Interrupt 11 ADC Conversion Complete
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procedure WDT_ISR; external name 'WDT_ISR'; // Interrupt 12 Watchdog Time-Out
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procedure INT1_ISR; external name 'INT1_ISR'; // Interrupt 13 External Interrupt 1
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procedure TIMER0_COMPA_ISR; external name 'TIMER0_COMPA_ISR'; // Interrupt 14 Timer/Counter0 Compare Match A
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procedure TIMER0_COMPB_ISR; external name 'TIMER0_COMPB_ISR'; // Interrupt 15 Timer/Counter0 Compare Match B
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procedure TIMER0_CAPT_ISR; external name 'TIMER0_CAPT_ISR'; // Interrupt 16 ADC Conversion Complete
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procedure TIMER1_COMPD_ISR; external name 'TIMER1_COMPD_ISR'; // Interrupt 17 Timer/Counter1 Compare Match D
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procedure FAULT_PROTECTION_ISR; external name 'FAULT_PROTECTION_ISR'; // Interrupt 18 Timer/Counter1 Fault Protection
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procedure _FPC_start; assembler; nostackframe; noreturn; public name '_START'; section '.init';
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asm
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rjmp __dtors_end
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rjmp INT0_ISR
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rjmp PCINT_ISR
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rjmp TIMER1_COMPA_ISR
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rjmp TIMER1_COMPB_ISR
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rjmp TIMER1_OVF_ISR
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rjmp TIMER0_OVF_ISR
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rjmp USI_START_ISR
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rjmp USI_OVF_ISR
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rjmp EE_RDY_ISR
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rjmp ANA_COMP_ISR
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rjmp ADC_ISR
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rjmp WDT_ISR
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rjmp INT1_ISR
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rjmp TIMER0_COMPA_ISR
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rjmp TIMER0_COMPB_ISR
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rjmp TIMER0_CAPT_ISR
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rjmp TIMER1_COMPD_ISR
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rjmp FAULT_PROTECTION_ISR
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.weak INT0_ISR
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.weak PCINT_ISR
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.weak TIMER1_COMPA_ISR
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.weak TIMER1_COMPB_ISR
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.weak TIMER1_OVF_ISR
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.weak TIMER0_OVF_ISR
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.weak USI_START_ISR
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.weak USI_OVF_ISR
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.weak EE_RDY_ISR
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.weak ANA_COMP_ISR
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.weak ADC_ISR
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.weak WDT_ISR
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.weak INT1_ISR
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.weak TIMER0_COMPA_ISR
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.weak TIMER0_COMPB_ISR
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.weak TIMER0_CAPT_ISR
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.weak TIMER1_COMPD_ISR
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.weak FAULT_PROTECTION_ISR
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.set INT0_ISR, Default_IRQ_handler
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.set PCINT_ISR, Default_IRQ_handler
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.set TIMER1_COMPA_ISR, Default_IRQ_handler
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.set TIMER1_COMPB_ISR, Default_IRQ_handler
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.set TIMER1_OVF_ISR, Default_IRQ_handler
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.set TIMER0_OVF_ISR, Default_IRQ_handler
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.set USI_START_ISR, Default_IRQ_handler
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.set USI_OVF_ISR, Default_IRQ_handler
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.set EE_RDY_ISR, Default_IRQ_handler
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.set ANA_COMP_ISR, Default_IRQ_handler
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.set ADC_ISR, Default_IRQ_handler
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.set WDT_ISR, Default_IRQ_handler
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.set INT1_ISR, Default_IRQ_handler
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.set TIMER0_COMPA_ISR, Default_IRQ_handler
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.set TIMER0_COMPB_ISR, Default_IRQ_handler
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.set TIMER0_CAPT_ISR, Default_IRQ_handler
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.set TIMER1_COMPD_ISR, Default_IRQ_handler
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.set FAULT_PROTECTION_ISR, Default_IRQ_handler
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end;
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end.
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