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https://gitlab.com/freepascal.org/fpc/source.git
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657b9a6203
Override register type for vectors to "integer registers" because we don't use mmregister on LLVM (they're all virtual, so it doesn't matter)
436 lines
14 KiB
ObjectPascal
436 lines
14 KiB
ObjectPascal
{
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Copyright (c) 2013 by Jonas Maebe
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Generate LLVM bytecode for add nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nllvmadd;
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{$i fpcdefs.inc}
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interface
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uses
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node,
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ncgadd;
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type
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tllvmaddnode = class(tcgaddnode)
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public
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function pass_1: tnode; override;
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procedure force_reg_left_right(allow_swap, allow_constant: boolean); override;
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protected
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procedure second_cmpsmallset; override;
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procedure second_cmpordinal; override;
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procedure second_add64bit; override;
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procedure second_cmp64bit; override;
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procedure second_addfloat; override;
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procedure second_cmpfloat; override;
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procedure second_opvector; override;
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end;
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implementation
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uses
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verbose,globtype,globals,cutils,
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aasmdata,
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symconst,symtype,symdef,defutil,
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llvmbase,aasmllvm,aasmllvmmetadata,
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cgbase,cgutils,pass_1,
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hlcgobj,
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nadd,ncal,ncnv,ncon
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;
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{ tllvmaddnode }
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function tllvmaddnode.pass_1: tnode;
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var
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exceptmode: ansistring;
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intrname: string;
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iscompcurrency: boolean;
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begin
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result:=inherited pass_1;
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if not assigned(result) and
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is_fpu(left.resultdef) and
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not(cs_opt_fastmath in current_settings.optimizerswitches) then
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begin
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case nodetype of
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addn:
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begin
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intrname:='LLVM_EXPERIMENTAL_CONSTRAINED_FADD';
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end;
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subn:
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begin
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intrname:='LLVM_EXPERIMENTAL_CONSTRAINED_FSUB';
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end;
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muln:
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begin
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intrname:='LLVM_EXPERIMENTAL_CONSTRAINED_FMUL';
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end;
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slashn:
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begin
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intrname:='LLVM_EXPERIMENTAL_CONSTRAINED_FDIV';
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end;
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else
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begin
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intrname:='';
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end;
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end;
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if intrname<>'' then
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begin
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iscompcurrency:=tfloatdef(left.resultdef).floattype in [s64currency,s64comp];
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if iscompcurrency then
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begin
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inserttypeconv_internal(left,s80floattype);
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inserttypeconv_internal(right,s80floattype);
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end;
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exceptmode:=llvm_constrainedexceptmodestring;
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result:=ccallnode.createintern(intrname,
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ccallparanode.create(cstringconstnode.createpchar(ansistring2pchar(exceptmode),length(exceptmode),llvm_metadatatype),
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ccallparanode.create(cstringconstnode.createpchar(ansistring2pchar('round.dynamic'),length('round.dynamic'),llvm_metadatatype),
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ccallparanode.create(right,
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ccallparanode.create(left,nil)
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)
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)
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)
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);
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if iscompcurrency then
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begin
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result:=ctypeconvnode.create_internal(result,resultdef);
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end;
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left:=nil;
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right:=nil;
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exit;
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end;
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end;
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{ there are no flags in LLVM }
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if expectloc=LOC_FLAGS then
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expectloc:=LOC_REGISTER;
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end;
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procedure tllvmaddnode.force_reg_left_right(allow_swap, allow_constant: boolean);
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begin
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{ comparison with pointer -> no immediate, as icmp can't handle pointer
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immediates (except for nil as "null", but we don't generate that) }
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if (nodetype in [equaln,unequaln,gtn,gten,ltn,lten]) and
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(is_address(left.resultdef) or
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is_address(right.resultdef)) then
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allow_constant:=false;
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inherited;
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{ pointer - pointer = integer -> make all defs integer since we can't
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subtract pointers }
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if (nodetype=subn) and
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is_address(left.resultdef) and
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is_address(right.resultdef) then
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begin
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,true);
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end
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{ pointer +/- integer -> make defs the same since a_op_* only gets a
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single type as argument }
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else if (nodetype in [addn,subn]) and
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(is_address(left.resultdef)<>is_address(right.resultdef)) then
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begin
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{ the result is a pointerdef -> typecast both arguments to pointer;
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a_op_*_reg will convert them back to integer as needed }
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if not is_address(left.resultdef) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,true);
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if not is_address(right.resultdef) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,resultdef,true);
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end;
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end;
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procedure tllvmaddnode.second_cmpsmallset;
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var
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tmpreg,
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tmpreg2: tregister;
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cmpop : topcmp;
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begin
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pass_left_right;
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location_reset(location,LOC_REGISTER,OS_8);
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location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,llvmbool1type);
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force_reg_left_right(false,false);
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case nodetype of
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equaln,
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unequaln:
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begin
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if nodetype=equaln then
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cmpop:=OC_EQ
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else
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cmpop:=OC_NE;
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_cond_size_reg_reg(la_icmp,
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location.register,cmpop,left.resultdef,left.location.register,right.location.register));
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end;
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lten,
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gten:
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begin
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if (not(nf_swapped in flags) and
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(nodetype = lten)) or
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((nf_swapped in flags) and
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(nodetype = gten)) then
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swapleftright;
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{ set1<=set2 <-> set2 and not(set1) = 0 }
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
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hlcg.a_op_reg_reg(current_asmdata.CurrAsmList,OP_NOT,left.resultdef,left.location.register,tmpreg);
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tmpreg2:=hlcg.getintregister(current_asmdata.CurrAsmList,left.resultdef);
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hlcg.a_op_reg_reg_reg(current_asmdata.CurrAsmList,OP_AND,left.resultdef,right.location.register,tmpreg,tmpreg2);
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_cond_size_reg_const(la_icmp,
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location.register,OC_EQ,left.resultdef,tmpreg2,0));
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end;
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else
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internalerror(2012042701);
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end;
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_load_reg_reg(current_asmdata.CurrAsmList,llvmbool1type,resultdef,location.register,tmpreg);
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location.register:=tmpreg;
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end;
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procedure tllvmaddnode.second_cmpordinal;
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var
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tmpreg: tregister;
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cmpop: topcmp;
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unsigned : boolean;
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begin
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pass_left_right;
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force_reg_left_right(true,true);
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unsigned:=not(is_signed(left.resultdef)) or
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not(is_signed(right.resultdef));
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case nodetype of
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ltn:
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if unsigned then
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cmpop:=OC_B
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else
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cmpop:=OC_LT;
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lten:
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if unsigned then
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cmpop:=OC_BE
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else
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cmpop:=OC_LTE;
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gtn:
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if unsigned then
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cmpop:=OC_A
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else
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cmpop:=OC_GT;
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gten:
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if unsigned then
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cmpop:=OC_AE
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else
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cmpop:=OC_GTE;
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equaln:
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cmpop:=OC_EQ;
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unequaln:
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cmpop:=OC_NE;
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else
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internalerror(2015031505);
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end;
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if nf_swapped in flags then
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cmpop:=swap_opcmp(cmpop);
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location_reset(location,LOC_REGISTER,OS_8);
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location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,llvmbool1type);
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if right.location.loc=LOC_CONSTANT then
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_cond_size_reg_const(la_icmp,
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location.register,cmpop,left.resultdef,left.location.register,right.location.value64))
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else
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_cond_size_reg_reg(la_icmp,
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location.register,cmpop,left.resultdef,left.location.register,right.location.register));
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_load_reg_reg(current_asmdata.CurrAsmList,llvmbool1type,resultdef,location.register,tmpreg);
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location.register:=tmpreg;
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end;
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procedure tllvmaddnode.second_add64bit;
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begin
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second_addordinal;
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end;
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procedure tllvmaddnode.second_cmp64bit;
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begin
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second_cmpordinal;
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end;
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procedure tllvmaddnode.second_addfloat;
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var
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tmpreg: tregister;
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op : tllvmop;
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llvmfpcmp : tllvmfpcmp;
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size : tdef;
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begin
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pass_left_right;
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{ get the operands in the correct order; there are no special cases here,
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everything is register-based }
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if nf_swapped in flags then
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swapleftright;
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{ put both operands in a register }
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,right.location,right.resultdef,true);
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hlcg.location_force_fpureg(current_asmdata.CurrAsmList,left.location,left.resultdef,true);
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{ see comment in thlcgllvm.a_loadfpu_ref_reg }
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if tfloatdef(left.resultdef).floattype in [s64comp,s64currency] then
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size:=sc80floattype
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else
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size:=left.resultdef;
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if nodetype in [ltn,lten,gtn,gten,equaln,unequaln] then
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begin
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case nodetype of
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ltn:
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llvmfpcmp:=lfc_olt;
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lten:
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llvmfpcmp:=lfc_ole;
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gtn:
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llvmfpcmp:=lfc_ogt;
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gten:
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llvmfpcmp:=lfc_oge;
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equaln:
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llvmfpcmp:=lfc_oeq;
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unequaln:
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llvmfpcmp:=lfc_une;
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else
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internalerror(2015031506);
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end;
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location_reset(location,LOC_REGISTER,OS_8);
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location.register:=hlcg.getintregister(current_asmdata.CurrAsmList,llvmbool1type);
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_fpcond_size_reg_reg(la_fcmp ,
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location.register,llvmfpcmp,size,left.location.register,right.location.register));
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tmpreg:=hlcg.getintregister(current_asmdata.CurrAsmList,resultdef);
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hlcg.a_load_reg_reg(current_asmdata.CurrAsmList,llvmbool1type,resultdef,location.register,tmpreg);
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location.register:=tmpreg;
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end
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else
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begin
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case nodetype of
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addn :
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op:=la_fadd;
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muln :
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op:=la_fmul;
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subn :
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op:=la_fsub;
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slashn :
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op:=la_fdiv;
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else
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internalerror(2013102401);
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end;
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location_reset(location,LOC_FPUREGISTER,def_cgsize(resultdef));
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location.register:=hlcg.getfpuregister(current_asmdata.CurrAsmList,resultdef);
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_size_reg_reg(op,location.register,size,
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left.location.register,right.location.register))
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end;
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end;
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procedure tllvmaddnode.second_cmpfloat;
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begin
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second_addfloat;
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end;
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procedure tllvmaddnode.second_opvector;
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var
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lv, rv: tdef;
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hreg: tregister;
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tempref: treference;
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op: tllvmop;
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isfloat: boolean;
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begin
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if not is_vector(left.resultdef) or
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not is_vector(right.resultdef) or
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not is_vector(resultdef) or
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not tarraydef(resultdef).is_hwvector then
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internalerror(2022090710);
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pass_left_right;
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if (nf_swapped in flags) then
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swapleftright;
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isfloat:=tarraydef(left.resultdef).elementdef.typ=floatdef;
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case nodetype of
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addn :
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if isfloat then
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op:=la_fadd
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else
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op:=la_add;
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muln :
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if isfloat then
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op:=la_fmul
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else
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op:=la_mul;
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subn :
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if isfloat then
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op:=la_fsub
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else
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op:=la_sub;
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slashn :
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if isfloat then
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op:=la_fdiv
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else if is_signed(tarraydef(left.resultdef).elementdef) then
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op:=la_sdiv
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else
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op:=la_udiv;
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xorn:
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if not isfloat then
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op:=la_xor
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else
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internalerror(2022090711);
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orn:
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if not isfloat then
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op:=la_or
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else
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internalerror(2022090712);
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andn:
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if not isfloat then
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op:=la_and
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else
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internalerror(2022090712);
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else
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internalerror(200610073);
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end;
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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lv:=to_hwvectordef(tarraydef(left.resultdef),false);
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rv:=to_hwvectordef(tarraydef(right.resultdef),false);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,lv,false);
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hlcg.location_force_reg(current_asmdata.CurrAsmList,right.location,right.resultdef,rv,false);
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location.register:=hlcg.getregisterfordef(current_asmdata.CurrAsmList,resultdef);
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current_asmdata.CurrAsmList.concat(taillvm.op_reg_size_reg_reg(op,location.register,lv,left.location.register,right.location.register));
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end;
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begin
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caddnode:=tllvmaddnode;
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end.
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