mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-07 18:47:52 +02:00
1060 lines
35 KiB
ObjectPascal
1060 lines
35 KiB
ObjectPascal
{
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Copyright (c) 2006 by Florian Klaempfl
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This unit implements the common part of the code generator for the Risc-V
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit cgrv;
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{$i fpcdefs.inc}
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interface
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uses
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globtype,symtype,symdef,
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cgbase,cgobj,
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aasmbase,aasmcpu,aasmtai,aasmdata,
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cpubase,cpuinfo,cgutils,rgcpu,
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parabase;
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type
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{ tcgrv }
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tcgrv = class(tcg)
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procedure a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : tcgpara); override;
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procedure a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; srcsize, dstsize: tcgsize; src, dst: TRegister); override;
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procedure a_call_reg(list : TAsmList;reg: tregister); override;
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procedure a_call_name(list : TAsmList;const s : string; weak: boolean); override;
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procedure a_load_const_ref(list: TAsmList; size: tcgsize; a: tcgint; const ref: treference); override;
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procedure a_load_reg_ref(list: TAsmList; fromsize, tosize: TCGSize; reg: tregister; const ref: treference); override;
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procedure a_load_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister); override;
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procedure a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister); override;
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procedure a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister); override;
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procedure a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister); override;
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procedure a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister); override;
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procedure a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);override;
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procedure a_cmp_const_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;a : tcgint;reg : tregister; l : tasmlabel); override;
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procedure a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp;reg1,reg2 : tregister;l : tasmlabel); override;
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procedure a_jmp_name(list : TAsmList;const s : string); override;
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procedure a_jmp_always(list : TAsmList;l: tasmlabel); override;
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procedure g_proc_entry(list : TAsmList;localsize : longint;nostackframe:boolean);override;
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procedure g_proc_exit(list : TAsmList;parasize : longint;nostackframe:boolean); override;
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procedure g_save_registers(list: TAsmList); override;
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procedure g_restore_registers(list: TAsmList); override;
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procedure g_profilecode(list: TAsmList); override;
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{ fpu move instructions }
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procedure a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister); override;
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procedure a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister); override;
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procedure a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference); override;
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procedure g_check_for_fpu_exception(list: TAsmList;force,clear : boolean); override;
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protected
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function fixref(list: TAsmList; var ref: treference): boolean;
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procedure maybeadjustresult(list: TAsmList; op: topcg; size: tcgsize; dst: tregister);
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end;
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const
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TOpCmp2AsmCond: Array[topcmp] of TAsmCond = (C_NONE,C_EQ,C_NONE,
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C_LT,C_GE,C_None,C_NE,C_NONE,C_LTU,C_GEU,C_NONE);
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const
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TOpCG2AsmConstOp: Array[topcg] of TAsmOp = (A_NONE,
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A_NONE,A_ADDI,A_ANDI,A_NONE,A_NONE,A_NONE,A_NONE,
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A_None,A_None,A_ORI,A_SRAI,A_SLLI,A_SRLI,A_NONE,A_XORI,A_None,A_None);
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TOpCG2AsmOp: Array[topcg] of TAsmOp = (A_NONE,
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A_NONE,A_ADD,A_AND,A_DIVU,A_DIV,A_MUL,A_MUL,
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A_None,A_None,A_OR,A_SRA,A_SLL,A_SRL,A_SUB,A_XOR,A_None,A_None);
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{$ifdef extdebug}
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function ref2string(const ref : treference) : string;
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function cgop2string(const op : TOpCg) : String;
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{$endif extdebug}
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implementation
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uses
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{$ifdef extdebug}sysutils,{$endif}
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globals,verbose,systems,cutils,
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symconst,symsym,symtable,fmodule,
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rgobj,tgobj,cpupi,procinfo,paramgr;
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{$ifdef extdebug}
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function ref2string(const ref : treference) : string;
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begin
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result := 'base : ' + inttostr(ord(ref.base)) + ' index : ' + inttostr(ord(ref.index)) + ' refaddr : ' + inttostr(ord(ref.refaddr)) + ' offset : ' + inttostr(ref.offset) + ' symbol : ';
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if (assigned(ref.symbol)) then
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result := result + ref.symbol.name;
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end;
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function cgop2string(const op : TOpCg) : String;
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const
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opcg_strings : array[TOpCg] of string[6] = (
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'None', 'Move', 'Add', 'And', 'Div', 'IDiv', 'IMul', 'Mul',
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'Neg', 'Not', 'Or', 'Sar', 'Shl', 'Shr', 'Sub', 'Xor', 'Rol', 'Ror'
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);
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begin
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result := opcg_strings[op];
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end;
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{$endif extdebug}
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procedure tcgrv.a_call_name(list : TAsmList;const s : string; weak: boolean);
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var
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href: treference;
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l: TAsmLabel;
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begin
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if not(weak) then
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reference_reset_symbol(href,current_asmdata.RefAsmSymbol(s,AT_FUNCTION),0,0,[])
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else
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reference_reset_symbol(href,current_asmdata.WeakRefAsmSymbol(s,AT_FUNCTION),0,0,[]);
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if cs_create_pic in current_settings.moduleswitches then
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begin
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href.refaddr:=addr_plt;
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list.concat(taicpu.op_ref(A_CALL,href));
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end
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else
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begin
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current_asmdata.getjumplabel(l);
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a_label(list,l);
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href.refaddr:=addr_pcrel_hi20;
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list.concat(taicpu.op_reg_ref(A_AUIPC,NR_RETURN_ADDRESS_REG,href));
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reference_reset_symbol(href,l,0,0,[]);
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href.refaddr:=addr_pcrel_lo12;
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list.concat(taicpu.op_reg_reg_ref(A_JALR,NR_RETURN_ADDRESS_REG,NR_RETURN_ADDRESS_REG,href));
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end;
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{ not assigned while generating external wrappers }
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if assigned(current_procinfo) then
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include(current_procinfo.flags,pi_do_call);
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end;
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procedure tcgrv.a_load_const_ref(list: TAsmList; size: tcgsize; a: tcgint; const ref: treference);
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begin
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if a=0 then
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a_load_reg_ref(list,size,size,NR_X0,ref)
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else
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inherited a_load_const_ref(list, size, a, ref);
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end;
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procedure tcgrv.a_loadaddr_ref_cgpara(list : TAsmList;const r : treference;const paraloc : tcgpara);
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var
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ref: treference;
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tmpreg: tregister;
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begin
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paraloc.check_simple_location;
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paramanager.allocparaloc(list,paraloc.location);
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case paraloc.location^.loc of
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LOC_REGISTER,LOC_CREGISTER:
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a_loadaddr_ref_reg(list,r,paraloc.location^.register);
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LOC_REFERENCE:
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begin
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reference_reset(ref,paraloc.alignment,[]);
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ref.base := paraloc.location^.reference.index;
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ref.offset := paraloc.location^.reference.offset;
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tmpreg := rg[R_INTREGISTER].getregister(list,R_SUBWHOLE);
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a_loadaddr_ref_reg(list,r,tmpreg);
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a_load_reg_ref(list,OS_ADDR,OS_ADDR,tmpreg,ref);
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end;
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else
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internalerror(2002080701);
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end;
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end;
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procedure tcgrv.a_bit_scan_reg_reg(list: TAsmList; reverse: boolean; srcsize, dstsize: tcgsize; src, dst: TRegister);
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begin
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internalerror(2016060401);
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end;
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procedure tcgrv.a_op_const_reg(list : TAsmList; Op: TOpCG; size: TCGSize; a: tcgint; reg: TRegister);
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begin
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a_op_const_reg_reg(list,op,size,a,reg,reg);
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end;
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procedure tcgrv.a_op_reg_reg(list : TAsmList; Op: TOpCG; size: TCGSize; src, dst: TRegister);
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begin
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a_op_reg_reg_reg(list,op,size,src,dst,dst);
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end;
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procedure tcgrv.a_op_const_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; a: tcgint; src, dst: tregister);
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var
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tmpreg: TRegister;
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begin
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optimize_op_const(size,op,a);
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if op=OP_NONE then
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begin
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a_load_reg_reg(list,size,size,src,dst);
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exit;
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end;
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if op=OP_SUB then
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begin
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op:=OP_ADD;
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a:=-a;
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end;
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{$ifdef RISCV64}
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if (op=OP_SHL) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_const(A_SLLIW,dst,src,a));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SHR) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_const(A_SRLIW,dst,src,a));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SAR) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_const(A_SRAIW,dst,src,a));
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maybeadjustresult(list,op,size,dst);
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end
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else
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{$endif RISCV64}
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if (TOpCG2AsmConstOp[op]<>A_None) and
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is_imm12(a) then
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begin
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list.concat(taicpu.op_reg_reg_const(TOpCG2AsmConstOp[op],dst,src,a));
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maybeadjustresult(list,op,size,dst);
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end
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else
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begin
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tmpreg:=getintregister(list,size);
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a_load_const_reg(list,size,a,tmpreg);
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a_op_reg_reg_reg(list,op,size,tmpreg,src,dst);
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end;
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end;
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procedure tcgrv.a_op_reg_reg_reg(list: TAsmList; op: TOpCg; size: tcgsize; src1, src2, dst: tregister);
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var
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name: String;
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pd: tprocdef;
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paraloc1, paraloc2: tcgpara;
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begin
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if op=OP_NOT then
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begin
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list.concat(taicpu.op_reg_reg_const(A_XORI,dst,src1,-1));
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maybeadjustresult(list,op,size,dst);
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end
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else if op=OP_NEG then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SUB,dst,NR_X0,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else
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case op of
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OP_MOVE:
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a_load_reg_reg(list,size,size,src1,dst);
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else
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{$ifdef RISCV64}
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if (op=OP_SHL) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SLLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SHR) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRLW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else if (op=OP_SAR) and
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(size=OS_S32) then
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begin
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list.concat(taicpu.op_reg_reg_reg(A_SRAW,dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end
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else
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{$endif RISCV64}
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if (op in [OP_IMUL,OP_MUL]) and not(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
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begin
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case size of
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OS_8:
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name:='fpc_mul_byte';
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OS_S8:
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name:='fpc_mul_shortint';
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OS_16:
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name:='fpc_mul_word';
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OS_S16:
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name:='fpc_mul_integer';
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OS_32:
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name:='fpc_mul_dword';
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OS_S32:
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name:='fpc_mul_longint';
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else
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Internalerror(2021030601);
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end;
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// if check_overflow then
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// name:=name+'_checkoverflow';
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pd:=search_system_proc(name);
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paraloc1.init;
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paraloc2.init;
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paramanager.getcgtempparaloc(list,pd,1,paraloc1);
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paramanager.getcgtempparaloc(list,pd,2,paraloc2);
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a_load_reg_cgpara(list,OS_8,src1,paraloc2);
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a_load_reg_cgpara(list,OS_8,src2,paraloc1);
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paramanager.freecgpara(list,paraloc2);
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paramanager.freecgpara(list,paraloc1);
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alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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a_call_name(list,upper(name),false);
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dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
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cg.a_reg_alloc(list,NR_FUNCTION_RESULT_REG);
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cg.a_load_reg_reg(list,size,size,NR_FUNCTION_RESULT_REG,dst);
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cg.a_reg_dealloc(list,NR_FUNCTION_RESULT_REG);
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paraloc2.done;
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paraloc1.done;
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end
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else
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begin
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list.concat(taicpu.op_reg_reg_reg(TOpCG2AsmOp[op],dst,src2,src1));
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maybeadjustresult(list,op,size,dst);
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end;
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end;
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end;
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procedure tcgrv.a_loadaddr_ref_reg(list : TAsmList;const ref : treference;r : tregister);
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var
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href: treference;
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b, tmpreg: TRegister;
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l: TAsmLabel;
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begin
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href:=ref;
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fixref(list,href);
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if (not assigned(href.symbol)) and
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(href.offset=0) then
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a_load_reg_reg(list,OS_ADDR,OS_ADDR,href.base,r)
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else if (assigned(href.symbol) or
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(not is_imm12(href.offset))) and
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(href.base<>NR_NO) then
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begin
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b:= href.base;
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current_asmdata.getjumplabel(l);
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a_label(list,l);
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href.base:=NR_NO;
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href.refaddr:=addr_pcrel_hi20;
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list.concat(taicpu.op_reg_ref(A_AUIPC,r,href));
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reference_reset_symbol(href,l,0,0,ref.volatility);
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href.refaddr:=addr_pcrel_lo12;
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list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,r,href));
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list.concat(taicpu.op_reg_reg_reg(A_ADD,r,r,b));
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end
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else if is_imm12(href.offset) and
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(href.base<>NR_NO) then
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begin
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list.concat(taicpu.op_reg_reg_const(A_ADDI,r,href.base,href.offset));
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end
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else if (href.refaddr=addr_pcrel) then
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begin
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tmpreg:=getintregister(list,OS_ADDR);
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b:=href.base;
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href.base:=NR_NO;
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current_asmdata.getjumplabel(l);
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a_label(list,l);
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href.refaddr:=addr_pcrel_hi20;
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list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
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reference_reset_symbol(href,l,0,0,ref.volatility);
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href.refaddr:=addr_pcrel_lo12;
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list.concat(taicpu.op_reg_reg_ref(A_ADDI,r,tmpreg,href));
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if b<>NR_NO then
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list.concat(taicpu.op_reg_reg_reg(A_ADD,r,r,b));
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end
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else
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internalerror(2016060504);
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end;
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procedure tcgrv.a_cmp_const_reg_label(list: TAsmList; size: tcgsize; cmp_op: topcmp; a: tcgint; reg: tregister; l: tasmlabel);
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begin
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if a=0 then
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a_cmp_reg_reg_label(list,size,cmp_op,NR_X0,reg,l)
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else
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inherited;
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end;
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procedure tcgrv.a_cmp_reg_reg_label(list : TAsmList;size : tcgsize;cmp_op : topcmp; reg1,reg2 : tregister;l : tasmlabel);
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var
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tmpreg: TRegister;
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ai: taicpu;
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begin
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if TOpCmp2AsmCond[cmp_op]=C_None then
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begin
|
|
cmp_op:=swap_opcmp(cmp_op);
|
|
tmpreg:=reg1;
|
|
reg1:=reg2;
|
|
reg2:=tmpreg;
|
|
end;
|
|
|
|
ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,reg2,reg1,l,0);
|
|
ai.is_jmp:=true;
|
|
ai.condition:=TOpCmp2AsmCond[cmp_op];
|
|
list.concat(ai);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_jmp_name(list : TAsmList;const s : string);
|
|
var
|
|
ai: taicpu;
|
|
href: treference;
|
|
tmpreg: TRegister;
|
|
l: TAsmLabel;
|
|
begin
|
|
reference_reset_symbol(href,current_asmdata.RefAsmSymbol(s,AT_FUNCTION),0,0,[]);
|
|
|
|
tmpreg:=getintregister(list,OS_ADDR);
|
|
|
|
current_asmdata.getjumplabel(l);
|
|
a_label(list,l);
|
|
|
|
href.refaddr:=addr_pcrel_hi20;
|
|
list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
|
|
reference_reset_symbol(href,l,0,0,[]);
|
|
href.refaddr:=addr_pcrel_lo12;
|
|
ai:=taicpu.op_reg_reg_ref(A_JALR,NR_X0,tmpreg,href);
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);
|
|
|
|
//ai:=taicpu.op_reg_sym(A_JAL,NR_X0,current_asmdata.RefAsmSymbol(s));
|
|
//ai.is_jmp:=true;
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_jmp_always(list : TAsmList;l: tasmlabel);
|
|
var
|
|
ai: taicpu;
|
|
{href: treference;
|
|
tmpreg: TRegister;}
|
|
begin
|
|
{reference_reset_symbol(href,l,0,0);
|
|
|
|
tmpreg:=getintregister(list,OS_ADDR);
|
|
|
|
current_asmdata.getjumplabel(l);
|
|
a_label(list,l);
|
|
|
|
href.refaddr:=addr_pcrel_hi20;
|
|
list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
|
|
reference_reset_symbol(href,l,0,0);
|
|
href.refaddr:=addr_pcrel_lo12;
|
|
ai:=taicpu.op_reg_reg_ref(A_JALR,NR_X0,tmpreg,href);
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);}
|
|
|
|
ai:=taicpu.op_reg_sym(A_JAL,NR_X0,l);
|
|
ai.is_jmp:=true;
|
|
list.concat(ai);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_proc_entry(list: TAsmList; localsize: longint; nostackframe: boolean);
|
|
const
|
|
{$ifdef cpu64bitalu}
|
|
store_int_op = A_SD;
|
|
{$else cpu64bitalu}
|
|
store_int_op = A_SW;
|
|
{$endif cpu64bitalu}
|
|
var
|
|
regs, fregs: tcpuregisterset;
|
|
r: TSuperRegister;
|
|
href: treference;
|
|
stackcount, stackAdjust: longint;
|
|
begin
|
|
if not(nostackframe) then
|
|
begin
|
|
a_reg_alloc(list,NR_STACK_POINTER_REG);
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
a_reg_alloc(list,NR_FRAME_POINTER_REG);
|
|
|
|
{ Int registers }
|
|
regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
|
|
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
regs:=regs+[RS_FRAME_POINTER_REG,RS_RETURN_ADDRESS_REG];
|
|
|
|
if (pi_do_call in current_procinfo.flags) then
|
|
regs:=regs+[RS_RETURN_ADDRESS_REG];
|
|
|
|
stackcount:=0;
|
|
for r:=RS_X0 to RS_X31 do
|
|
if r in regs then
|
|
inc(stackcount,sizeof(pint));
|
|
|
|
{ Float registers }
|
|
fregs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
|
|
for r:=RS_F0 to RS_F31 do
|
|
if r in fregs then
|
|
inc(stackcount,8);
|
|
|
|
inc(localsize,stackcount);
|
|
if not is_imm12(-localsize) then
|
|
begin
|
|
if not (RS_RETURN_ADDRESS_REG in regs) then
|
|
begin
|
|
include(regs,RS_RETURN_ADDRESS_REG);
|
|
inc(localsize,sizeof(pint));
|
|
end;
|
|
end;
|
|
|
|
reference_reset_base(href,NR_STACK_POINTER_REG,stackcount,ctempposinvalid,0,[]);
|
|
|
|
stackAdjust:=0;
|
|
if stackcount>0 then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,-stackcount));
|
|
stackAdjust:=stackcount;
|
|
dec(localsize,stackcount);
|
|
end;
|
|
|
|
for r:=RS_X0 to RS_X31 do
|
|
if r in regs then
|
|
begin
|
|
dec(href.offset,sizeof(pint));
|
|
list.concat(taicpu.op_reg_ref(store_int_op,newreg(R_INTREGISTER,r,R_SUBWHOLE),href));
|
|
end;
|
|
|
|
{ Float registers }
|
|
for r:=RS_F0 to RS_F31 do
|
|
if r in fregs then
|
|
begin
|
|
dec(href.offset,8);
|
|
list.concat(taicpu.op_reg_ref(A_FSD,newreg(R_FPUREGISTER,r,R_SUBWHOLE),href));
|
|
end;
|
|
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_FRAME_POINTER_REG,NR_STACK_POINTER_REG,stackAdjust));
|
|
|
|
if localsize>0 then
|
|
begin
|
|
localsize:=align(localsize,sizeof(pint));
|
|
|
|
if is_imm12(-localsize) then
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,-localsize))
|
|
else
|
|
begin
|
|
a_load_const_reg(list,OS_INT,localsize,NR_RETURN_ADDRESS_REG);
|
|
list.concat(taicpu.op_reg_reg_reg(A_SUB,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_RETURN_ADDRESS_REG));
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_proc_exit(list: TAsmList; parasize: longint; nostackframe: boolean);
|
|
const
|
|
{$ifdef cpu64bitalu}
|
|
load_op = A_LD;
|
|
{$else cpu64bitalu}
|
|
load_op = A_LW;
|
|
{$endif cpu64bitalu}
|
|
var
|
|
r: tsuperregister;
|
|
regs, fregs: tcpuregisterset;
|
|
stacksize, localsize, precompensation, postcompensation: longint;
|
|
href: treference;
|
|
begin
|
|
if not(nostackframe) then
|
|
begin
|
|
regs:=rg[R_INTREGISTER].used_in_proc-paramanager.get_volatile_registers_int(pocall_stdcall);
|
|
|
|
if current_procinfo.framepointer<>NR_STACK_POINTER_REG then
|
|
regs:=regs+[RS_FRAME_POINTER_REG,RS_RETURN_ADDRESS_REG];
|
|
|
|
if (pi_do_call in current_procinfo.flags) then
|
|
regs:=regs+[RS_RETURN_ADDRESS_REG];
|
|
|
|
stacksize:=0;
|
|
for r:=RS_X31 downto RS_X0 do
|
|
if r in regs then
|
|
inc(stacksize,sizeof(pint));
|
|
|
|
{ Float registers }
|
|
fregs:=rg[R_FPUREGISTER].used_in_proc-paramanager.get_volatile_registers_fpu(pocall_stdcall);
|
|
for r:=RS_F0 to RS_F31 do
|
|
if r in fregs then
|
|
inc(stacksize,8);
|
|
|
|
localsize:=current_procinfo.calc_stackframe_size+stacksize;
|
|
if localsize>0 then
|
|
begin
|
|
localsize:=align(localsize,sizeof(pint));
|
|
|
|
if not is_imm12(-localsize) then
|
|
begin
|
|
if not (RS_RETURN_ADDRESS_REG in regs) then
|
|
begin
|
|
include(regs,RS_RETURN_ADDRESS_REG);
|
|
inc(localsize,sizeof(pint));
|
|
inc(stacksize,sizeof(pint));
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
if not is_imm12(localsize) then
|
|
begin
|
|
precompensation:=localsize-2032;
|
|
postcompensation:=localsize-precompensation;
|
|
end
|
|
else
|
|
begin
|
|
precompensation:=0;
|
|
postcompensation:=localsize;
|
|
end;
|
|
|
|
reference_reset_base(href,NR_STACK_POINTER_REG,postcompensation-stacksize,ctempposinvalid,0,[]);
|
|
|
|
if precompensation>0 then
|
|
begin
|
|
if is_imm12(precompensation) then
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,precompensation))
|
|
else
|
|
begin
|
|
{ use X12 as temporary register as it is not callee-saved }
|
|
a_load_const_reg(list,OS_INT,precompensation,NR_X12);
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,NR_X12));
|
|
end;
|
|
end;
|
|
|
|
{ Float registers }
|
|
for r:=RS_F31 downto RS_F0 do
|
|
if r in fregs then
|
|
begin
|
|
list.concat(taicpu.op_reg_ref(A_FLD,newreg(R_FPUREGISTER,r,R_SUBWHOLE),href));
|
|
inc(href.offset,8);
|
|
end;
|
|
|
|
for r:=RS_X31 downto RS_X0 do
|
|
if r in regs then
|
|
begin
|
|
list.concat(taicpu.op_reg_ref(load_op,newreg(R_INTREGISTER,r,R_SUBWHOLE),href));
|
|
inc(href.offset,sizeof(pint));
|
|
end;
|
|
|
|
if postcompensation>0 then
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_STACK_POINTER_REG,NR_STACK_POINTER_REG,postcompensation));
|
|
end;
|
|
|
|
if (target_info.system in (systems_freertos+systems_embedded)) and (po_interrupt in current_procinfo.procdef.procoptions) then
|
|
begin
|
|
list.concat(Taicpu.Op_none(A_MRET));
|
|
end
|
|
else
|
|
list.concat(taicpu.op_reg_reg(A_JALR,NR_X0,NR_RETURN_ADDRESS_REG));
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_save_registers(list: TAsmList);
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_restore_registers(list: TAsmList);
|
|
begin
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_profilecode(list: TAsmList);
|
|
begin
|
|
if target_info.system in [system_riscv32_linux,system_riscv64_linux] then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,NR_X10,NR_RETURN_ADDRESS_REG,0));
|
|
a_call_name(list,'_mcount',false);
|
|
end
|
|
else
|
|
internalerror(2018092201);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_call_reg(list : TAsmList;reg: tregister);
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(A_JALR,NR_RETURN_ADDRESS_REG,reg));
|
|
include(current_procinfo.flags,pi_do_call);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_load_reg_ref(list: TAsmList; fromsize, tosize: TCGSize;
|
|
reg: tregister; const ref: treference);
|
|
|
|
const
|
|
StoreInstr: array[OS_8..OS_INT] of TAsmOp =
|
|
(A_SB,A_SH,A_SW
|
|
{$ifdef cpu64bitalu}
|
|
,
|
|
A_SD
|
|
{$endif cpu64bitalu}
|
|
);
|
|
var
|
|
ref2: TReference;
|
|
tmpreg: tregister;
|
|
op: TAsmOp;
|
|
begin
|
|
if not (fromsize in [OS_8..OS_INT,OS_S8..OS_SINT]) then
|
|
internalerror(2002090904);
|
|
if not (tosize in [OS_8..OS_INT,OS_S8..OS_SINT]) then
|
|
internalerror(2002090905);
|
|
|
|
tosize:=tcgsize2unsigned[tosize];
|
|
|
|
ref2 := ref;
|
|
fixref(list, ref2);
|
|
|
|
op := storeinstr[tcgsize2unsigned[tosize]];
|
|
list.concat(taicpu.op_reg_ref(op, reg,ref2));
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_load_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister);
|
|
var
|
|
href: treference;
|
|
op: TAsmOp;
|
|
tmpreg: TRegister;
|
|
begin
|
|
href:=ref;
|
|
fixref(list,href);
|
|
|
|
if href.refaddr=addr_pcrel then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_ADDR);
|
|
a_loadaddr_ref_reg(list,href,tmpreg);
|
|
reference_reset_base(href,tmpreg,0,ctempposinvalid,0,ref.volatility);
|
|
end;
|
|
|
|
case fromsize of
|
|
OS_8: op:=A_LBU;
|
|
OS_16: op:=A_LHU;
|
|
OS_S8: op:=A_LB;
|
|
OS_S16: op:=A_LH;
|
|
{$ifdef RISCV64}
|
|
OS_32: op:=A_LWU;
|
|
OS_S32: op:=A_LW;
|
|
OS_64,
|
|
OS_S64: op:=A_LD;
|
|
{$else}
|
|
OS_64,OS_S64, { This only happens if tosize is smaller than fromsize }
|
|
{ We can therefore only consider the low 32-bit of the 64bit value }
|
|
OS_32,
|
|
OS_S32: op:=A_LW;
|
|
{$endif}
|
|
else
|
|
internalerror(2016060502);
|
|
end;
|
|
|
|
list.concat(taicpu.op_reg_ref(op,reg,href));
|
|
if (fromsize<>tosize) and (not (tosize in [OS_SINT,OS_INT])) then
|
|
a_load_reg_reg(list,fromsize,tosize,reg,reg);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_load_const_reg(list: TAsmList; size: tcgsize; a: tcgint; register: tregister);
|
|
begin
|
|
if a=0 then
|
|
a_load_reg_reg(list,size,size,NR_X0,register)
|
|
else
|
|
begin
|
|
if is_imm12(a) then
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,register,NR_X0,a))
|
|
else if is_lui_imm(a) then
|
|
list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF))
|
|
else
|
|
begin
|
|
if (a and $800)<>0 then
|
|
list.concat(taicpu.op_reg_const(A_LUI,register,((a shr 12)+1) and $FFFFF))
|
|
else
|
|
list.concat(taicpu.op_reg_const(A_LUI,register,(a shr 12) and $FFFFF));
|
|
|
|
list.concat(taicpu.op_reg_reg_const(A_ADDI,register,register,SarSmallint(smallint(a shl 4),4)));
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_loadfpu_reg_reg(list: TAsmList; fromsize, tosize: tcgsize; reg1, reg2: tregister);
|
|
var
|
|
op: TAsmOp;
|
|
ai: taicpu;
|
|
|
|
const
|
|
convOp: array[OS_F32..OS_F64,OS_F32..OS_F64] of TAsmOp =
|
|
((A_None,A_FCVT_D_S),
|
|
(A_FCVT_S_D,A_None));
|
|
|
|
begin
|
|
if fromsize<>tosize then
|
|
begin
|
|
list.concat(taicpu.op_reg_reg(convOp[fromsize,tosize],reg2,reg1));
|
|
maybe_check_for_fpu_exception(list);
|
|
end
|
|
else
|
|
begin
|
|
if tosize=OS_F32 then
|
|
op:=A_FSGNJ_S
|
|
else
|
|
op:=A_FSGNJ_D;
|
|
|
|
ai:=taicpu.op_reg_reg_reg(op,reg2,reg1,reg1);
|
|
list.concat(ai);
|
|
rg[R_FPUREGISTER].add_move_instruction(ai);
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_loadfpu_ref_reg(list: TAsmList; fromsize, tosize: tcgsize; const ref: treference; reg: tregister);
|
|
var
|
|
href: treference;
|
|
op: TAsmOp;
|
|
tmpreg: TRegister;
|
|
l: TAsmLabel;
|
|
begin
|
|
href:=ref;
|
|
fixref(list,href);
|
|
|
|
if href.refaddr=addr_pcrel then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_ADDR);
|
|
a_loadaddr_ref_reg(list,href,tmpreg);
|
|
reference_reset_base(href,tmpreg,0,ctempposinvalid,0,ref.volatility);
|
|
end;
|
|
|
|
if fromsize=OS_F32 then
|
|
op:=A_FLW
|
|
else
|
|
op:=A_FLD;
|
|
|
|
list.concat(taicpu.op_reg_ref(op,reg,href));
|
|
|
|
if fromsize<>tosize then
|
|
a_loadfpu_reg_reg(list,fromsize,tosize,reg,reg);
|
|
end;
|
|
|
|
|
|
procedure tcgrv.a_loadfpu_reg_ref(list: TAsmList; fromsize, tosize: tcgsize; reg: tregister; const ref: treference);
|
|
var
|
|
href: treference;
|
|
op: TAsmOp;
|
|
tmpreg: TRegister;
|
|
begin
|
|
href:=ref;
|
|
fixref(list,href);
|
|
|
|
if href.refaddr=addr_pcrel then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_ADDR);
|
|
a_loadaddr_ref_reg(list,href,tmpreg);
|
|
reference_reset_base(href,tmpreg,0,ctempposinvalid,0,ref.volatility);
|
|
end;
|
|
|
|
if fromsize<>tosize then
|
|
begin
|
|
tmpreg:=getfpuregister(list,tosize);
|
|
a_loadfpu_reg_reg(list,fromsize,tosize,reg,tmpreg);
|
|
reg:=tmpreg;
|
|
end;
|
|
|
|
if tosize=OS_F32 then
|
|
op:=A_FSW
|
|
else
|
|
op:=A_FSD;
|
|
|
|
list.concat(taicpu.op_reg_ref(op,reg,href));
|
|
end;
|
|
|
|
|
|
function tcgrv.fixref(list: TAsmList; var ref: treference): boolean;
|
|
var
|
|
tmpreg: TRegister;
|
|
href: treference;
|
|
l: TAsmLabel;
|
|
begin
|
|
result:=true;
|
|
|
|
if ref.refaddr=addr_pcrel then
|
|
exit;
|
|
|
|
if assigned(ref.symbol) then
|
|
begin
|
|
if cs_create_pic in current_settings.moduleswitches then
|
|
begin
|
|
reference_reset_symbol(href,ref.symbol,0,0,[]);
|
|
ref.symbol:=nil;
|
|
|
|
tmpreg:=getintregister(list,OS_INT);
|
|
|
|
current_asmdata.getaddrlabel(l);
|
|
a_label(list,l);
|
|
|
|
href.refaddr:=addr_got_pcrel_hi;
|
|
list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
|
|
reference_reset_symbol(href,l,0,0,[]);
|
|
href.refaddr:=addr_pcrel_lo12;
|
|
href.base:=tmpreg;
|
|
{$ifdef RISCV64}
|
|
list.concat(taicpu.op_reg_ref(A_LD,tmpreg,href));
|
|
{$else}
|
|
list.concat(taicpu.op_reg_ref(A_LW,tmpreg,href));
|
|
{$endif}
|
|
end
|
|
else
|
|
begin
|
|
reference_reset_symbol(href,ref.symbol,ref.offset,ref.alignment,ref.volatility);
|
|
ref.symbol:=nil;
|
|
ref.offset:=0;
|
|
|
|
tmpreg:=getintregister(list,OS_INT);
|
|
|
|
current_asmdata.getaddrlabel(l);
|
|
a_label(list,l);
|
|
|
|
href.refaddr:=addr_pcrel_hi20;
|
|
list.concat(taicpu.op_reg_ref(A_AUIPC,tmpreg,href));
|
|
reference_reset_symbol(href,l,0,0,ref.volatility);
|
|
href.refaddr:=addr_pcrel_lo12;
|
|
list.concat(taicpu.op_reg_reg_ref(A_ADDI,tmpreg,tmpreg,href));
|
|
end;
|
|
|
|
if (ref.index<>NR_NO) and
|
|
(ref.base<>NR_NO) then
|
|
begin
|
|
a_op_reg_reg(list,OP_ADD,OS_INT,ref.base,tmpreg);
|
|
ref.base:=tmpreg;
|
|
end
|
|
else if (ref.index=NR_NO) and
|
|
(ref.base<>NR_NO) then
|
|
ref.index:=tmpreg
|
|
else
|
|
ref.base:=tmpreg;
|
|
end
|
|
else if (ref.index=NR_NO) and
|
|
(ref.base=NR_NO) then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_INT);
|
|
|
|
a_load_const_reg(list, OS_ADDR,ref.offset,tmpreg);
|
|
|
|
reference_reset_base(ref,tmpreg,0,ctempposinvalid,ref.alignment,ref.volatility);
|
|
end;
|
|
|
|
if (ref.index<>NR_NO) and
|
|
(ref.base=NR_NO) then
|
|
begin
|
|
ref.base:=ref.index;
|
|
ref.index:=NR_NO;
|
|
end;
|
|
|
|
if not is_imm12(ref.offset) then
|
|
begin
|
|
tmpreg:=getintregister(list,OS_INT);
|
|
a_load_const_reg(list,OS_INT,ref.offset,tmpreg);
|
|
|
|
ref.offset:=0;
|
|
|
|
if (ref.index<>NR_NO) and
|
|
(ref.base<>NR_NO) then
|
|
begin
|
|
a_op_reg_reg(list,OP_ADD,OS_INT,ref.index,tmpreg);
|
|
ref.index:=tmpreg;
|
|
end
|
|
else
|
|
ref.index:=tmpreg;
|
|
end;
|
|
|
|
if (ref.index<>NR_NO) and
|
|
(ref.base<>NR_NO) then
|
|
begin
|
|
tmpreg:=getaddressregister(list);
|
|
list.concat(taicpu.op_reg_reg_reg(A_ADD,tmpreg,ref.base,ref.index));
|
|
ref.base:=tmpreg;
|
|
ref.index:=NR_NO;
|
|
end;
|
|
end;
|
|
|
|
|
|
procedure tcgrv.maybeadjustresult(list: TAsmList; op: topcg; size: tcgsize; dst: tregister);
|
|
const
|
|
overflowops = [OP_MUL,OP_IMUL,OP_SHL,OP_ADD,OP_SUB,OP_NOT,OP_NEG];
|
|
begin
|
|
if (op in overflowops) and
|
|
(size in [OS_8,OS_S8,OS_16,OS_S16{$ifdef RISCV64},OS_32,OS_S32{$endif RISCV64}]) then
|
|
a_load_reg_reg(list,OS_INT,size,dst,dst)
|
|
end;
|
|
|
|
|
|
procedure tcgrv.g_check_for_fpu_exception(list: TAsmList;force,clear : boolean);
|
|
var
|
|
r : TRegister;
|
|
ai: taicpu;
|
|
l: TAsmLabel;
|
|
begin
|
|
if needs_check_for_fpu_exceptions then
|
|
begin
|
|
r:=getintregister(list,OS_INT);
|
|
list.concat(taicpu.op_reg(A_FRFLAGS,r));
|
|
current_asmdata.getjumplabel(l);
|
|
ai:=taicpu.op_reg_reg_sym_ofs(A_Bxx,r,NR_X0,l,0);
|
|
ai.is_jmp:=true;
|
|
ai.condition:=C_EQ;
|
|
list.concat(ai);
|
|
alloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
cg.a_call_name(current_asmdata.CurrAsmList,'FPC_THROWFPUEXCEPTION',false);
|
|
dealloccpuregisters(list,R_INTREGISTER,paramanager.get_volatile_registers_int(pocall_default));
|
|
a_label(list,l);
|
|
end;
|
|
end;
|
|
|
|
end.
|