mirror of
https://gitlab.com/freepascal.org/fpc/source.git
synced 2025-04-06 23:28:28 +02:00
a7c0fa0def
+ Added postfix parsing in tattreader.GetToken
- Removed all postfixed versions of OpCodes from the instruction list
+ Added all missing OpCodes from Xtensa ISA
* Changed branch OpCode to A_B, similar to ARM
+ Added missing branch condition flags BCI and BSI
* Updated existing compiler code that referred to the old postfixed instructions
+ Added prefix and postfix handling in TxtensaInstrWriter.WriteInstruction
* Updated TCPUAddNode.second_addfloat to specify .S postfix
* Updated tcpuunaryminusnode.second_float to specify .S postfix
+ Implemented prefix and postfix identification in txtensaattreader.is_asmopcode
* Adapted branch condition extraction to respect postfixes
* Changed itcpugas to call findreg_by_name_table from raatt.pas (same as issue #0037121, difficult to test these changes without including a fix for the register name search problem)
git-svn-id: trunk@45672 -
32 lines
359 B
ObjectPascal
32 lines
359 B
ObjectPascal
{ %cpu=xtensa }
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{ %norun }
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unit asmtest;
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interface
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procedure test;
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implementation
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procedure test; assembler;
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label
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lbl, lbl2;
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asm
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bbci.l a4, 7, lbl2
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_bnez.n a4, lbl2
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loopnez a5, lbl
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beqz.n a2, lbl
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add a4, a5, a6
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lbl:
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bt b9, lbl
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sub.s f1, f9, f13
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_loopgtz a3, lbl2
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rsr.prid a2
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extui a4, a3, 2, 1
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lbl2:
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mula.aa.ll a3, a4
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end;
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end.
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