mirror of
https://gitlab.com/freepascal.org/fpc/source.git
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aec49340a3
- Change spelling of AM_PREDRECEMENT to AM_PREDECREMENT
- Fix multiline comment style to use {}
- Fix indenting of code in method tcgavr.g_concatcopy
git-svn-id: trunk@49474 -
384 lines
20 KiB
ObjectPascal
384 lines
20 KiB
ObjectPascal
{
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Copyright (c) 1998-2003 by Carl Eric Codere and Peter Vreman
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Handles the common arm assembler reader routines
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit raavr;
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{$i fpcdefs.inc}
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interface
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uses
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cpubase,
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aasmtai,aasmdata,
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rautils,
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globtype;
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type
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TAVROperand=class(TOperand)
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end;
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TAVRInstruction=class(TInstruction)
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function ConcatInstruction(p:TAsmList) : tai;override;
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end;
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TRegType = (rt_all, rt_even, rt_16_31, rt_even_24_30, rt_16_23, rt_XYZ, rt_YZ, rt_X, rt_Y, rt_Z);
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TAVROpConstraint = record
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case typ : toptype of
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top_none : ();
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top_reg : (rt: TRegType; am: set of taddressmode; minconst, maxconst: tcgint);
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top_ref,
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top_const : (max, min: tcgint);
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end;
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// Constraints of operands per opcode
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// Encode variable number of operands by bit position, e.g.
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// 2 operands = 1 shl 2 = 4
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// 1 or 2 operands = 1 shl 1 + 1 shl 2 = 6
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TAVRInstrConstraint = record
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numOperands: byte;
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Operands: array[0..max_operands-1] of TAVROpConstraint;
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end;
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{$PUSH}
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{$WARN 3177 off : Some fields coming after "$1" were not initialized}
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const
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AVRInstrConstraint: array[TAsmOp] of TAVRInstrConstraint =
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// A_NONE
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((numOperands: 0; Operands: ((typ: top_none), (typ: top_none))),
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// A_ADD
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_ADC
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_ADIW
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_even_24_30), (typ: top_const; max: 63; min: 0))),
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// A_SUB
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_SUBI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_SBC
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_SBCI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_SBRC
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 7; min: 0))),
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// A_SBRS
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 7; min: 0))),
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// A_SBIW
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_even_24_30), (typ: top_const; max: 63; min: 0))),
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// A_AND
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_ANDI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_OR
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_ORI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_EOR
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_COM
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_NEG
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_SBR
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_CBR
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_INC
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_DEC
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_TST
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_MUL
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_MULS
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_reg; rt: rt_16_31))),
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// A_MULSU
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_23), (typ: top_reg; rt: rt_16_23))),
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// A_FMUL
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_23), (typ: top_reg; rt: rt_16_23))),
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// A_FMULS
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_23), (typ: top_reg; rt: rt_16_23))),
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// A_FMULSU
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_23), (typ: top_reg; rt: rt_16_23))),
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// A_RJMP
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 2047; min: -2048), (typ: top_reg; rt: rt_all))),
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// A_IJMP
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_EIJMP
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_JMP, max size depends on size op PC
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: (1 shl 22 - 1); min: 0), (typ: top_none))),
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// A_RCALL
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 2047; min: -2048), (typ: top_none))),
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// A_ICALL
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_EICALL
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CALL, max size depends on size op PC
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: (1 shl 22 - 1); min: 0), (typ: top_none))),
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// A_RET
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_IRET
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CPSE
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_CP
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_CPC
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_CPI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_SBIC
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 31; min: 0), (typ: top_const; max: 7; min: 0))),
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// A_SBIS
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 31; min: 0), (typ: top_const; max: 7; min: 0))),
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// A_BRxx
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 63; min: -64), (typ: top_none))),
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// A_MOV
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_all))),
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// A_MOVW
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_even), (typ: top_reg; rt: rt_even))),
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// A_LDI
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_const; max: 255; min: -128))),
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// A_LDS TODO: There are 2 versions with different machine codes and constant ranges. Could possibly distinguish based on size of PC?
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// Perhaps handle separately with a check on sub-architecture? Range check only important if smaller instruction code selected on larger arch
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 65535; min: 0))),
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// A_LD
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]))),
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// A_LDD
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63))),
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// A_STS TODO: See LDS above
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 65535; min: 0), (typ: top_reg; rt: rt_all))),
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// A_ST
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_XYZ; am: [AM_UNCHANGED, AM_POSTINCREMENT, AM_PREDECREMENT]), (typ: top_reg; rt: rt_all))),
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// A_STD
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_YZ; am: [AM_UNCHANGED]; minconst: 0; maxconst: 63), (typ: top_reg; rt: rt_all))),
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// A_LPM
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(numOperands: (1 shl 0 + 1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_Z; am: [AM_UNCHANGED, AM_POSTINCREMENT]))),
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// A_ELPM
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(numOperands: (1 shl 0 + 1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_reg; rt: rt_Z; am: [AM_UNCHANGED, AM_POSTINCREMENT]))),
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// A_SPM
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(numOperands: (1 shl 0 + 1 shl 1); Operands: ((typ: top_reg; rt: rt_Z; am: [AM_UNCHANGED, AM_POSTINCREMENT]), (typ: top_none))),
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// A_IN
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 63; min: 0))),
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// A_OUT
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 63; min: 0), (typ: top_reg; rt: rt_all))),
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// A_PUSH
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_POP
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_LSL
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_LSR
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_ROL
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_ROR
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_ASR
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_SWAP
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_BSET
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 7; min: 0), (typ: top_none))),
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// A_BCLR
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 7; min: 0), (typ: top_none))),
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// A_SBI
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 32; min: 0), (typ: top_const; max: 7; min: 0))),
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// A_CBI
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(numOperands: (1 shl 2); Operands: ((typ: top_const; max: 32; min: 0), (typ: top_const; max: 7; min: 0))),
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// A_SEC
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SEH
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SEI
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SEN
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SER
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_16_31), (typ: top_none))),
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// A_SES
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SET
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SEV
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SEZ
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLC
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLH
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLI
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLN
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLR
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(numOperands: (1 shl 1); Operands: ((typ: top_reg; rt: rt_all), (typ: top_none))),
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// A_CLS
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLT
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLV
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_CLZ
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_BST
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 7; min: 0))),
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// A_BLD
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_all), (typ: top_const; max: 7; min: 0))),
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// A_BREAK
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_NOP
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_SLEEP
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_WDR
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(numOperands: (1 shl 0); Operands: ((typ: top_none), (typ: top_none))),
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// A_XCH
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(numOperands: (1 shl 2); Operands: ((typ: top_reg; rt: rt_Z), (typ: top_reg; rt: rt_all))),
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// A_DES
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(numOperands: (1 shl 1); Operands: ((typ: top_const; max: 15; min: 0), (typ: top_none)))
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);
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{$POP}
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implementation
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uses
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aasmcpu, verbose, cgbase, itcpugas;
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function TAVRInstruction.ConcatInstruction(p:TAsmList) : tai;
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var
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i: integer;
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err, opregasref: boolean;
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s1, s2: string;
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reg: tregister;
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begin
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result:=inherited ConcatInstruction(p);
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if Result.typ = ait_instruction then
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begin
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// check if number of operands fall inside the allowed set
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if ((1 shl taicpu(Result).ops) and AVRInstrConstraint[opcode].numOperands = 0) then
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Message(asmr_e_invalid_opcode_and_operand)
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else
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begin
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for i := 0 to taicpu(Result).ops-1 do
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begin
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err := true;
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opregasref := false;
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// Type check
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if (taicpu(Result).oper[i]^.typ = AVRInstrConstraint[opcode].Operands[i].typ) then
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err := false
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// if label was specified check if const is expected
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else if (AVRInstrConstraint[opcode].Operands[i].typ = top_const) and (taicpu(Result).oper[i]^.typ = top_ref) then
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err := false
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// Also expressions such as X+, -Z and X+8 are classified as TOP_REF
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else if (AVRInstrConstraint[opcode].Operands[i].typ = top_reg) and (taicpu(Result).oper[i]^.typ = top_ref) and
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(int64(taicpu(Result).oper[i]^.ref^.base) and $01030000 > 0) then
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begin
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err := false;
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opregasref := true;
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reg := taicpu(Result).oper[i]^.ref^.base;
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end
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// LDD r1, a or STD a, r1 where a is local variable => type is set to top_local
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// also mov r10, TypeCastToByte(procParam) returns top_local for typecasted param
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// but no further information is available at this point to check
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else if (AVRInstrConstraint[opcode].Operands[i].typ = top_reg) and (taicpu(Result).oper[i]^.typ = top_local) and
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(opcode in [A_LDD, A_STD, A_MOV]) then
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begin
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err := false;
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end;
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if err then
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begin
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WriteStr(s1, taicpu(Result).oper[i]^.typ);
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WriteStr(s2, AVRInstrConstraint[opcode].Operands[i].typ);
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Message2(type_e_incompatible_types, s1, s2);
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end
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else if (taicpu(Result).oper[i]^.typ = top_reg) or opregasref then
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begin
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err := false;
|
|
if not opregasref then
|
|
reg := taicpu(Result).oper[i]^.reg;
|
|
|
|
case AVRInstrConstraint[opcode].Operands[i].rt of
|
|
rt_all: err := int64(reg) > $1030000; // excluding pointer registers X, Y, Z
|
|
rt_even: err := int64(reg) mod 2 = 1;
|
|
rt_even_24_30: err := not(word(reg) in [24, 26, 28, 30]);
|
|
rt_16_31: err := not(word(reg) in [16..31]);
|
|
rt_16_23: err := not(word(reg) in [16..23]);
|
|
rt_Z: err := (int64(reg) <> $0103001e);
|
|
rt_YZ: err := not((int64(reg) = $0103001c) or
|
|
(int64(reg) =$0103001e));
|
|
rt_XYZ: err := not((int64(reg) = $0103001a) or
|
|
(int64(reg) = $0103001c) or
|
|
(int64(reg) = $0103001e));
|
|
end;
|
|
|
|
// Catch erroneous z if it should be z+k or something similar
|
|
// By checking if .am is not empty (implying a reference is expected)
|
|
|
|
// ldd R20, z should not pass => opregasref = true
|
|
// but ldd R20, z+1 should pass => opregasref = false
|
|
if not (err) and (AVRInstrConstraint[opcode].Operands[i].am = [AM_UNCHANGED]) then
|
|
err := not opregasref;
|
|
|
|
if not (err) and not(AM_UNCHANGED in AVRInstrConstraint[opcode].Operands[i].am) and
|
|
((AM_POSTINCREMENT in AVRInstrConstraint[opcode].Operands[i].am) or
|
|
(AM_PREDECREMENT in AVRInstrConstraint[opcode].Operands[i].am)) then
|
|
err := not opregasref;
|
|
|
|
if not(err) and opregasref then
|
|
begin
|
|
if (taicpu(Result).oper[i]^.ref^.addressmode = AM_UNCHANGED) and
|
|
(AM_UNCHANGED in AVRInstrConstraint[opcode].Operands[i].am) then
|
|
err := ((taicpu(Result).oper[i]^.ref^.offset > AVRInstrConstraint[opcode].Operands[i].maxconst) or
|
|
(taicpu(Result).oper[i]^.ref^.offset < AVRInstrConstraint[opcode].Operands[i].minconst))
|
|
|
|
else if (taicpu(Result).oper[i]^.ref^.addressmode in AVRInstrConstraint[opcode].Operands[i].am) then
|
|
err := false
|
|
|
|
else
|
|
err := true;
|
|
end;
|
|
|
|
if err then
|
|
Message1(asmr_e_invalid_ref_register, gas_regname(reg));
|
|
end
|
|
else if taicpu(Result).oper[i]^.typ = top_const then
|
|
begin
|
|
// Need to check if original value was signed or simply sign overflowed in 16 bit?
|
|
if ((taicpu(Result).oper[i]^.val > AVRInstrConstraint[opcode].Operands[i].max) or
|
|
(taicpu(Result).oper[i]^.val < AVRInstrConstraint[opcode].Operands[i].min)) then
|
|
Message(asmr_e_constant_out_of_bounds);
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
end;
|
|
|
|
end.
|