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238 lines
8.7 KiB
ObjectPascal
238 lines
8.7 KiB
ObjectPascal
{
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Copyright (c) 1998-2002 by Florian Klaempfl
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Generate i386 assembler for math nodes
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit n386mat;
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{$i fpcdefs.inc}
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interface
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uses
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node,nmat,ncgmat,nx86mat;
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type
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ti386moddivnode = class(tx86moddivnode)
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procedure pass_generate_code;override;
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end;
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ti386shlshrnode = class(tx86shlshrnode)
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procedure second_64bit;override;
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function first_shlshr64bitint: tnode; override;
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end;
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ti386unaryminusnode = class(tx86unaryminusnode)
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end;
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ti386notnode = class(tx86notnode)
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end;
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implementation
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uses
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globtype,systems,constexp,
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cutils,verbose,globals,
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symconst,symdef,aasmbase,aasmtai,aasmdata,defutil,
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cgbase,pass_2,
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ncon,
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cpubase,cpuinfo,
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cga,ncgutil,cgobj,cgutils,
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hlcgobj;
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{*****************************************************************************
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TI386MODDIVNODE
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*****************************************************************************}
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procedure ti386moddivnode.pass_generate_code;
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var
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hreg1:Tregister;
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power:longint;
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hl:Tasmlabel;
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begin
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if is_64bitint(resultdef) then
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{ should be handled in pass_1 (JM) }
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internalerror(2001090507);
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if (nodetype=divn) and (right.nodetype=ordconstn) and
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is_signed(left.resultdef) and
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ispowerof2(tordconstnode(right).value.svalue,power) and
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((current_settings.optimizecputype = cpu_386) or
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(cs_opt_size in current_settings.optimizerswitches)) then
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begin
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{ signed divide-by-power-of-two optimized for size }
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secondpass(left);
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if codegenerror then
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exit;
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secondpass(right);
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if codegenerror then
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exit;
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg1:=left.location.register;
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_reg_reg(A_TEST,S_L,hreg1,hreg1);
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current_asmdata.getjumplabel(hl);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_NS,hl);
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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if power=1 then
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emit_reg(A_INC,S_L,hreg1)
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else
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emit_const_reg(A_ADD,S_L,tordconstnode(right).value.svalue-1,hreg1);
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cg.a_label(current_asmdata.CurrAsmList,hl);
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emit_const_reg(A_SAR,S_L,power,hreg1);
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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location.register:=hreg1;
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end
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else
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inherited pass_generate_code;
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end;
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{*****************************************************************************
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TI386SHLRSHRNODE
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*****************************************************************************}
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function ti386shlshrnode.first_shlshr64bitint: tnode;
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begin
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result := nil;
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end;
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procedure ti386shlshrnode.second_64bit;
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var
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hreg64hi,hreg64lo:Tregister;
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v : TConstExprInt;
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l2,l3:Tasmlabel;
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begin
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{ shifting by a constant directly coded: }
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if (right.nodetype=ordconstn) then
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begin
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v:=Tordconstnode(right).value and 63;
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{ load left operator in a register }
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if not(left.location.loc in [LOC_REGISTER,LOC_CREGISTER]) or
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((left.location.loc=LOC_CREGISTER) and ((v.svalue and 31)<>0)) then
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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location_reset(location,left.location.loc,def_cgsize(resultdef));
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if v>31 then
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begin
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if nodetype=shln then
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begin
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hreg64hi:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
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end
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else
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begin
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hreg64lo:=cg.getintregister(current_asmdata.CurrAsmList,OS_32);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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if ((v and 31) <> 0) then
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emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
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end;
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location.register64.reghi:=hreg64lo;
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location.register64.reglo:=hreg64hi;
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end
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else
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begin
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if (v.svalue and 31)<>0 then
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begin
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if nodetype=shln then
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begin
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emit_const_reg_reg(A_SHLD,S_L,v.svalue and 31,hreg64lo,hreg64hi);
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emit_const_reg(A_SHL,S_L,v.svalue and 31,hreg64lo);
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end
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else
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begin
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emit_const_reg_reg(A_SHRD,S_L,v.svalue and 31,hreg64hi,hreg64lo);
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emit_const_reg(A_SHR,S_L,v.svalue and 31,hreg64hi);
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end;
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end;
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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end;
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end
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else
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begin
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location_reset(location,LOC_REGISTER,def_cgsize(resultdef));
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{ load left operator in a register }
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hlcg.location_force_reg(current_asmdata.CurrAsmList,left.location,left.resultdef,resultdef,false);
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hreg64hi:=left.location.register64.reghi;
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hreg64lo:=left.location.register64.reglo;
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{ load right operators in a register }
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cg.getcpuregister(current_asmdata.CurrAsmList,NR_ECX);
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hlcg.a_load_loc_reg(current_asmdata.CurrAsmList,right.resultdef,u32inttype,right.location,NR_ECX);
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{ left operator is already in a register }
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{ hence are both in a register }
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{ is it in the case ECX ? }
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{ the damned shift instructions work only til a count of 32 }
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{ so we've to do some tricks here }
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current_asmdata.getjumplabel(l2);
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current_asmdata.getjumplabel(l3);
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cg.a_reg_alloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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emit_const_reg(A_TEST,S_B,32,NR_CL);
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cg.a_jmp_flags(current_asmdata.CurrAsmList,F_E,l2);
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cg.a_reg_dealloc(current_asmdata.CurrAsmList,NR_DEFAULTFLAGS);
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if nodetype=shln then
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begin
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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emit_reg_reg(A_MOV,S_L,hreg64lo,hreg64hi);
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emit_reg_reg(A_XOR,S_L,hreg64lo,hreg64lo);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l2);
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emit_reg_reg_reg(A_SHLD,S_L,NR_CL,hreg64lo,hreg64hi);
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emit_reg_reg(A_SHL,S_L,NR_CL,hreg64lo);
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end
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else
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begin
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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emit_reg_reg(A_MOV,S_L,hreg64hi,hreg64lo);
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emit_reg_reg(A_XOR,S_L,hreg64hi,hreg64hi);
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cg.a_jmp_always(current_asmdata.CurrAsmList,l3);
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cg.a_label(current_asmdata.CurrAsmList,l2);
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emit_reg_reg_reg(A_SHRD,S_L,NR_CL,hreg64hi,hreg64lo);
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emit_reg_reg(A_SHR,S_L,NR_CL,hreg64hi);
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end;
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cg.a_label(current_asmdata.CurrAsmList,l3);
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cg.ungetcpuregister(current_asmdata.CurrAsmList,NR_ECX);
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location.register64.reglo:=hreg64lo;
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location.register64.reghi:=hreg64hi;
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end;
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end;
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begin
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cunaryminusnode:=ti386unaryminusnode;
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cmoddivnode:=ti386moddivnode;
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cshlshrnode:=ti386shlshrnode;
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cnotnode:=ti386notnode;
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end.
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