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99 lines
2.5 KiB
ObjectPascal
99 lines
2.5 KiB
ObjectPascal
{
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Copyright (c) 2000-2002 by Florian Klaempfl and Jonas Maebe
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Code generation for add nodes on the Risc-V64
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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****************************************************************************
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}
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unit nrv64add;
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{$I fpcdefs.inc}
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interface
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uses
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node, ncgadd, aasmbase, nrvadd, cpubase;
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type
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trv64addnode = class(trvaddnode)
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protected
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function pass_1: tnode; override;
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procedure second_add64bit; override;
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function use_generic_mul32to64: boolean; override;
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end;
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implementation
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uses
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systems,
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cutils,verbose,
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paramgr,procinfo,
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aasmtai,aasmdata,aasmcpu,defutil,
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cgbase,cgcpu,cgutils,
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globals,
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pass_1,
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CPUInfo,cpupara,
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ncon,nset,nadd,
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symconst,
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hlcgobj, ncgutil,cgobj;
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function trv64addnode.pass_1: tnode;
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begin
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if (nodetype=muln) and
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(left.resultdef.typ=orddef) and (left.resultdef.typ=orddef) and
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(CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype]) then
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begin
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result:=nil;
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firstpass(left);
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firstpass(right);
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expectloc:=LOC_REGISTER;
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end
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else if (nodetype=muln) and
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(not (CPURV_HAS_MUL in cpu_capabilities[current_settings.cputype])) and
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(is_64bit(left.resultdef) or
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is_64bit(right.resultdef)) then
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begin
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result:=first_add64bitint;
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end
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else
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Result:=inherited pass_1;
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if expectloc=LOC_FLAGS then
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expectloc:=LOC_REGISTER;
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end;
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procedure trv64addnode.second_add64bit;
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begin
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second_addordinal;
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end;
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function trv64addnode.use_generic_mul32to64: boolean;
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begin
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result:=false;
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end;
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begin
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caddnode := trv64addnode;
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end.
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